Serial Peripheral Interface Bus

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Single Master to Single Slave : basic SPI bus example.

The Serial Peripheral Interface bus (SPI) is a synchronous serial communication interface specification used for short distance communication, primarily in embedded systems. The interface was developed by Motorola in the late eighties and has become a de facto standard. Typical applications include Secure Digital cards and liquid crystal displays.

SPI devices communicate in full duplex mode using a master-slave architecture with a single master. The master device originates the frame for reading and writing. Multiple slave devices are supported through selection with individual slave select (SS) lines.

Sometimes SPI is called a four-wire serial bus, contrasting with three-, two-, and one-wire serial buses. The SPI may be accurately described as a synchronous serial interface,[1] but it is different from the Synchronous Serial Interface (SSI) protocol, which is also a four-wire synchronous serial communication protocol. But SSI Protocol employs differential signaling and provides only a single simplex communication channel.


The SPI bus specifies four logic signals:

  • SCLK: Serial Clock (output from master).
  • MOSI: Master Output, Slave Input (output from master).
  • MISO: Master Input, Slave Output (output from slave).
  • S̅S̅: Slave Select (active low, output from master).

Alternative naming conventions are also widely used, and SPI port pin names for particular IC products may differ from those depicted in these illustrations:

Serial Clock:


Master Output Slave Input:


Master Input Slave Output:


Slave Select is often called "chip select" on the slave:

  • S̅S̅: C̅S̅, nCS, /CS, CS#, CS, CSB, CSN, EN, nSS, /SS, SS#, STE, SYNC, SSQ.

The MOSI/MISO convention requires that, on devices using the alternate names, SDI on the master be connected to SDO on the slave, and vice versa. Chip select polarity is rarely active high, although some notations (such as SS or CS instead of nSS or nCS) suggest otherwise. Slave select is used instead of an addressing concept.


The SPI bus can operate with a single master device and with one or more slave devices.

If a single slave device is used, the SS pin may be fixed to logic low if the slave permits it. Some slaves require a falling edge of the chip select signal to initiate an action. An example is the Maxim MAX1242 ADC, which starts conversion on a high→low transition. With multiple slave devices, an independent SS signal is required from the master for each slave device.

Most slave devices have tri-state outputs so their MISO signal becomes high impedance (logically disconnected) when the device is not selected. Devices without tri-state outputs cannot share SPI bus segments with other devices; only one such slave could talk to the master.

Data transmission[edit]

A typical hardware setup using two shift registers to form an inter-chip circular buffer

To begin communication, the bus master configures the clock, using a frequency supported by the slave device, typically up to a few MHz. The master then selects the slave device with a logic level 0 on the select line. If a waiting period is required, such as for analog-to-digital conversion, the master must wait for at least that period of time before issuing clock cycles.

During each SPI clock cycle, a full duplex data transmission occurs. The master sends a bit on the MOSI line and the slave reads it, while the slave sends a bit on the MISO line and the master reads it. This sequence is maintained even when only one-directional data transfer is intended.

Transmissions normally involve two shift registers of some given word size, such as eight bits, one in the master and one in the slave; they are connected in a virtual ring topology. Data is usually shifted out with the most-significant bit first, while shifting a new least-significant bit into the same register. At the same time, Data from the counterpart is shifted into the least-significant bit register. After the register bits have been shifted out and in, the master and slave have exchanged register values. If more data needs to be exchanged, the shift registers are reloaded and the process repeats. Transmission may continue for any number of clock cycles. When complete, the master stops toggling the clock signal, and typically deselects the slave.

Transmissions often consist of 8-bit words. However, other word sizes are also common, for example, 16-bit words for touchscreen controllers or audio codecs, such as the TSC2101 by Texas Instruments, or 12-bit words for many digital-to-analog or analog-to-digital converters.

Every slave on the bus that has not been activated using its chip select line must disregard the input clock and MOSI signals, and must not drive MISO.

Clock polarity and phase[edit]

A timing diagram showing clock polarity and phase. The red vertical line represents CPHA=0 and the blue vertical line represents CPHA=1

In addition to setting the clock frequency, the master must also configure the clock polarity and phase with respect to the data. Motorola SPI Block Guide[3] names these two options as CPOL and CPHA respectively, and most vendors have adopted that convention.

The timing diagram is shown to the right. The timing is further described below and applies to both the master and the slave device.

  • At CPOL=0 the base value of the clock is zero, i.e. the idle state is 0 and active state is 1.
    • For CPHA=0, data are captured on the clock's rising edge (low→high transition) and data is output on a falling edge (high→low clock transition).
    • For CPHA=1, data are captured on the clock's falling edge and data is output on a rising edge.
  • At CPOL=1 the base value of the clock is one (inversion of CPOL=0), i.e. the idle state is 1 and active state is 0.
    • For CPHA=0, data are captured on clock's falling edge and data is output on a rising edge.
    • For CPHA=1, data are captured on clock's rising edge and data is output on a falling edge.

That is, CPHA=0 means sampling on the first clock edge, while CPHA=1 means sampling on the second clock edge, regardless of whether that clock edge is rising or falling. Note that with CPHA=0, the data must be stable for a half cycle before the first clock cycle.

In other words, CPHA=0 means transmitting data on the active to idle state and CPHA=1 means that data is transmitted on the idle to active state edge. Or put another way, CPHA=0 means capturing (i.e recording in a input register) on the idle to active state edge and CPHA=1 means that data is captured on the active to idle state edge.

Note that if transmission happens on a particular edge, then capturing will happen on the opposite edge(i.e. if transmission happens on falling, then reception happens on rising and vice versa). The MOSI and MISO signals are usually stable (at their reception points) for the half cycle until the next clock transition. SPI master and slave devices may well sample data at different points in that half cycle.

This adds more flexibility to the communication channel between the master and slave.

Mode numbers[edit]

The combinations of polarity and phases are often referred to as modes which are commonly numbered according to the following convention, with CPOL as the high order bit and CPHA as the low order bit:

For "Microchip PIC" / "ARM-based" microcontrollers (note that NCPHA is the inversion of CPHA):

SPI Mode Clock Polarity
Clock Phase
Clock Edge
0 0 0 1
1 0 1 0
2 1 0 1
3 1 1 0

For PIC32MX : SPI mode configure CKP,CKE and SMP bits.Set SMP bit,and CKP,CKE two bits configured as above table.

For other microcontrollers:

0 0 0
1 0 1
2 1 0
3 1 1

Another commonly used notation represents the mode as a (CPOL, CPHA) tuple; e.g., the value '(0, 1)' would indicate CPOL=0 and CPHA=1.

Independent slave configuration[edit]

Typical SPI bus: master and three independent slaves

In the independent slave configuration, there is an independent chip select line for each slave. A pull-up resistor between power source and chip select line is highly recommended for each independent device to reduce cross-talk between devices.[4] This is the way SPI is normally used. Since the MISO pins of the slaves are connected together, they are required to be tri-state pins (high, low or high-impedance).

Daisy chain configuration[edit]

Daisy-chained SPI bus: master and cooperative slaves

Some products that implement SPI may be connected in a daisy chain configuration, the first slave output being connected to the second slave input, etc. The SPI port of each slave is designed to send out during the second group of clock pulses an exact copy of the data it received during the first group of clock pulses. The whole chain acts as a communication shift register; daisy chaining is often done with shift registers to provide a bank of inputs or outputs through SPI. Such a feature only requires a single SS line from the master, rather than a separate SS line for each slave.[5]

Applications that require a daisy chain configuration include SGPIO and JTAG.

Valid communications[edit]

Some slave devices are designed to ignore any SPI communications in which the number of clock pulses is greater than specified. Others do not care, ignoring extra inputs and continuing to shift the same output bit. It is common for different devices to use SPI communications with different lengths, as, for example, when SPI is used to access the scan chain of a digital IC by issuing a command word of one size (perhaps 32 bits) and then getting a response of a different size (perhaps 153 bits, one for each pin in that scan chain).


SPI devices sometimes use another signal line to send an interrupt signal to a host CPU. Examples include pen-down interrupts from touchscreen sensors, thermal limit alerts from temperature sensors, alarms issued by real time clock chips, SDIO,[6] and headset jack insertions from the sound codec in a cell phone. Interrupts are not covered by the SPI standard; their usage is neither forbidden nor specified by the standard.

Example of bit-banging the master protocol[edit]

Below is an example of bit-banging the SPI protocol as an SPI master with CPOL=0, CPHA=0, and eight bits per transfer. The example is written in the C programming language. Because this is CPOL=0 the clock must be pulled low before the chip select is activated. The chip select line must be activated, which normally means being toggled low, for the peripheral before the start of the transfer, and then deactivated afterwards. Most peripherals allow or require several transfers while the select line is low; this routine might be called several times before deselecting the chip.

 * Simultaneously transmit and receive a byte on the SPI.
 * Polarity and phase are assumed to be both 0, i.e.:
 *   - input data is captured on rising edge of SCLK.
 *   - output data is propagated on falling edge of SCLK.
 * Returns the received byte.
uint8_t SPI_transfer_byte(uint8_t byte_out)
    uint8_t byte_in = 0;
    uint8_t bit;

    for (bit = 0x80; bit; bit >>= 1) {
        /* Shift-out a bit to the MOSI line */
        write_MOSI((byte_out & bit) ? HIGH : LOW);

        /* Delay for at least the peer's setup time */

        /* Pull the clock line high */

        /* Shift-in a bit from the MISO line */
        if (read_MISO() == HIGH)
            byte_in |= bit;

        /* Delay for at least the peer's hold time */

        /* Pull the clock line low */

    return byte_in;

Pros and cons[edit]


  • Full duplex communication in the default version of this protocol.
  • Push-pull drivers (as opposed to open drain) provide good signal integrity and high speed
  • Higher throughput than I²C or SMBus
  • Complete protocol flexibility for the bits transferred
    • Not limited to 8-bit words
    • Arbitrary choice of message size, content, and purpose
  • Extremely simple hardware interfacing
    • Typically lower power requirements than I²C or SMBus due to less circuitry (including pull up resistors)
    • No arbitration or associated failure modes
    • Slaves use the master's clock, and do not need precision oscillators
    • Slaves do not need a unique address — unlike I²C or GPIB or SCSI
    • Transceivers are not needed
  • Uses only four pins on IC packages, and wires in board layouts or connectors, much fewer than parallel interfaces
  • At most one unique bus signal per device (chip select); all others are shared
  • Signals are unidirectional allowing for easy Galvanic isolation
  • Not limited to any maximum clock speed, enabling potentially high speed
  • Simple software implementation


  • Requires more pins on IC packages than I²C, even in the three-wire variant
  • No in-band addressing; out-of-band chip select signals are required on shared buses
  • No hardware flow control by the slave (but the master can delay the next clock edge to slow the transfer rate)
  • No hardware slave acknowledgment (the master could be transmitting to nowhere and not know it)
  • Typically supports only one master device (depends on device's hardware implementation)
  • No error-checking protocol is defined
  • Without a formal standard, validating conformance is not possible
  • Only handles short distances compared to RS-232, RS-485, or CAN-bus. (its distance can be extended with use of transceivers like RS-422)
  • Many existing variations, making it difficult to find development tools like host adapters that support those variations
  • SPI does not support hot swapping (dynamically adding nodes).
  • Interrupts must either be implemented with out-of-band signals or be faked by using periodic polling similarly to USB 1.1 and 2.0
  • Some variants like Multi I/O SPI and three-wire serial buses defined below are half-duplex.


The board real estate savings compared to a parallel I/O bus are significant, and have earned SPI a solid role in embedded systems. That is true for most system-on-a-chip processors, both with higher end 32-bit processors such as those using ARM, MIPS, or PowerPC and with other microcontrollers such as the AVR, PIC, and MSP430. These chips usually include SPI controllers capable of running in either master or slave mode. In-system programmable AVR controllers (including blank ones) can be programmed using an SPI interface.[7]

Chip or FPGA based designs sometimes use SPI to communicate between internal components; on-chip real estate can be as costly as its on-board cousin.

The full-duplex capability makes SPI very simple and efficient for single master/single slave applications. Some devices use the full-duplex mode to implement an efficient, swift data stream for applications such as digital audio, digital signal processing, or telecommunications channels, but most off-the-shelf chips stick to half-duplex request/response protocols.

SPI is used to talk to a variety of peripherals, such as

For high performance systems, FPGAs sometimes use SPI to interface as a slave to a host, as a master to sensors, or for flash memory used to bootstrap if they are SRAM-based.

Although there are some similarities between the SPI bus and the JTAG (IEEE 1149.1-2013) protocol, they are not interchangeable. The SPI bus is intended for high speed, on board initialization of device peripherals, while the JTAG protocol is intended to provide reliable test access to the I/O pins from an off board controller with less precise signal delay and skew parameters. While not strictly a level sensitive interface, the JTAG protocol supports the recovery of both setup and hold violations between JTAG devices by reducing the clock rate or changing the clock's duty cycles. Consequently, the JTAG interface is not intended to support extremely high data rates.[8]

SGPIO is essentially another (incompatible) application stack for SPI designed for particular backplane management activities.[citation needed] SGPIO uses 3-bit messages.


The SPI bus is a de facto standard. However, the lack of a formal standard is reflected in a wide variety of protocol options. Different word sizes are common. Every device defines its own protocol, including whether it supports commands at all. Some devices are transmit-only; others are receive-only. Chip selects are sometimes active-high rather than active-low. Some protocols send the least significant bit first.

Some devices even have minor variances from the CPOL/CPHA modes described above. Sending data from slave to master may use the opposite clock edge as master to slave. Devices often require extra clock idle time before the first clock or after the last one, or between a command and its response. Some devices have two clocks, one to read data, and another to transmit it into the device. Many of the read clocks run from the chip select line.

Some devices require an additional flow control signal from slave to master, indicating when data are ready. This leads to a 5-wire protocol instead of the usual 4. Such a ready or enable signal is often active-low, and needs to be enabled at key points such as after commands or between words. Without such a signal, data transfer rates may need to be slowed down significantly, or protocols may need to have dummy bytes inserted, to accommodate the worst case for the slave response time. Examples include initiating an ADC conversion, addressing the right page of flash memory, and processing enough of a command that device firmware can load the first word of the response. (Many SPI masters do not support that signal directly, and instead rely on fixed delays.)

Many SPI chips only support messages that are multiples of 8 bits. Such chips can not interoperate with the JTAG or SGPIO protocols, or any other protocol that requires messages that are not multiples of 8 bits.

There are also hardware-level differences. Some chips combine MOSI and MISO into a single data line (SI/SO); this is sometimes called 'three-wire' signaling (in contrast to normal 'four-wire' SPI). Another variation of SPI removes the chip select line, managing protocol state machine entry/exit using other methods. Anyone needing an external connector for SPI defines their own: UEXT, JTAG connector, Secure Digital card socket, etc. Signal levels depend entirely on the chips involved.

SafeSPI[9] is an industry standard for SPI in automotive applications. Its main focus is the transmission of sensor data between different devices.

Development tools[edit]

When developing or troubleshooting systems using SPI, visibility at the level of hardware signals can be important.

Host adapters[edit]

There are a number of USB hardware solutions to provide computers, running Linux, Mac, or Windows, SPI master and/or slave capabilities. Many of them also provide scripting and/or programming capabilities (Visual Basic, C/C++, VHDL etc.).

An SPI host adapter lets the user play the role of a master on an SPI bus directly from PC. They are used for embedded systems, chips (FPGA/ASIC/SoC) and peripheral testing, programming and debugging.

The key parameters of SPI adapters are: the maximum supported frequency for the serial interface, command-to-command latency and the maximum length for SPI commands. It is possible to find SPI adapters on the market today that support up to 100 MHz serial interfaces, with virtually unlimited access length.

SPI protocol being a de facto standard, some SPI host adapters also have the ability of supporting other protocols beyond the traditional 4-wires SPI (for example, support of quad-SPI protocol or other custom serial protocol that derive from SPI[10]).

Examples of SPI host adapters (in manufacturers alphabetical order):

Manufacturer SPI host adapter Host bus Bus protocol support Max frequency
Byte Paradigm SPI Storm USB SPI, dual/quad, custom 100 MHz
Corelis BusPro-S USB SPI, dual/quad 60 MHz
HydraBus HydraBus-HydraFW USB I²C, 2-Wire, 3-Wire, JTAG, CAN, UART, Parallel, Scriptable binary bitbang, SPI 42 MHz/varies
Microchip MCP2210 Kit USB SPI 12 MHz
National Instruments USB-8452 USB I²C, SPI 50 MHz
Total Phase Cheetah SPI Host Adapter USB SPI 40 MHz
Total Phase Promira Serial Platform USB, Ethernet I²C, SPI, single/dual/quad, and eSPI 80 MHz
Dangerous Prototypes Bus Pirate USB 1-Wire, I2C, SPI, JTAG*, Asynchronous serial, Scriptable binary bitbang, UART varies

Protocol analyzers[edit]

SPI protocol analyzers are tools which sample an SPI bus and decode the electrical signals to provide a higher-level view of the data being transmitted on a specific bus.

Examples of SPI protocol analyzers (in manufacturers alphabetical order):

Manufacturer Analyser model Host bus Bus protocol support Max sample rate Extras
Saleae Logic Pro 16 USB SPI, I2C, serial, custom 500 Mega-samples/second Analog (50 Mega-samples/second)
TechTools DigiView Logic Analyzers USB SPI, I2C, CAN, Async, Sync, I2S, State, Custom 500 Mega-samples/second Extendable with custom plugins
Total Phase Beagle I2C/SPI Protocol Analyzer USB SPI, I2C, MDIO 50 Mega-samples/second
Total Phase Promira Serial Platform USB, Ethernet eSPI


Most oscilloscope vendors offer oscilloscope-based triggering and protocol decoding for SPI. Most support 2-, 3-, and 4-wire SPI. The triggering and decoding capability is typically offered as an optional extra. SPI signals can be accessed via analog oscilloscope channels or with digital MSO channels.[11]

Logic analyzers[edit]

When developing and/or troubleshooting the SPI bus, examination of hardware signals can be very important. Logic analyzers are tools which collect, analyze, decode, and store signals so people can view the high-speed waveforms at their leisure. Logic analyzers display time-stamps of each signal level change, which can help find protocol problems. Most logic analyzers have the capability to decode bus signals into high-level protocol data and show ASCII data.

Related terms[edit]

Intelligent SPI controllers[edit]

A queued serial peripheral interface (QSPI) is a type of SPI controller that uses a data queue to transfer data across the SPI bus.[12] It has a wrap-around mode allowing continuous transfers to and from the queue with only intermittent attention from the CPU. Consequently, the peripherals appear to the CPU as memory-mapped parallel devices. This feature is useful in applications such as control of an A/D converter. Other programmable features in QSPI are chip selects and transfer length/delay.

SPI controllers from different vendors support different feature sets; such DMA queues are not uncommon, although they may be associated with separate DMA engines rather than the SPI controller itself, such as used by multichannel buffered serial port (MCBSP).[13] Most SPI master controllers integrate support for up to four chip selects,[14] although some require chip selects to be managed separately through GPIO lines.


Microwire,[15] often spelled μWire, is essentially a predecessor of SPI and a trademark of National Semiconductor. It's a strict subset of SPI: half-duplex, and using SPI mode 0. Microwire chips tend to need slower clock rates than newer SPI versions; perhaps 2 MHz vs. 20 MHz. Some Microwire chips also support a three-wire mode, which fits neatly with the restriction to half-duplex.


Microwire/Plus[16] is an enhancement of Microwire and features full-duplex communication and support for SPI modes 0 and 1. There was no specified improvement in serial clock speed.

Three-wire serial buses[edit]

As mentioned, one variant of SPI uses single bidirectional data line (slave out/slave in, called SISO) instead of two unidirectional ones (MOSI and MISO). This variant is restricted to a half duplex mode. It tends to be used for lower performance parts, such as small EEPROMs used only during system startup and certain sensors, and Microwire. Few SPI master controllers support this mode; although it can often be easily bit-banged in software.

Dual SPI[edit]

Because the full-duplex nature of SPI is rarely used, an extension uses both data pins in a half-duplex configuration to send two bits per clock cycle. Typically a command byte is sent requesting a response in dual mode, after which the MOSI line becomes SIO0 (serial I/O 0) and carries even bits, while the MISO line becomes SIO1 and carries odd bits. Data is still transmitted msbit-first, but SIO1 carries bits 7, 5, 3 and 1 of each byte, while SIO0 carries bits 6, 4, 2 and 0.

This is particularly popular among SPI ROMs, which have to send a large amount of data, and comes in two variants:[17][18]

  • Dual read commands accept the send and address from the master in single mode, and return the data in dual mode
  • Dual I/O commands send the command in single mode, then send the address and return data in dual mode.

Quad SPI[edit]

While dual SPI re-uses the existing serial I/O lines, quad SPI adds two more I/O lines (SIO2 and SIO3) and sends 4 data bits per clock cycle. Again, it is requested by special commands, which enable quad mode after the command itself is sent in single mode.[17][18]


Futher extendeding quad SPI, some devices support a "quad everything" mode where all communication takes place over 4 data lines, including commands.[19] This is variously called "QPI"[18] (not to be confused with Intel QuickPath Interconnect) or "serial quad I/O" (SQI)[20]

This requires programming a configuration bit in the device and requires care after reset to establish communication.

Double data rate[edit]

In addition to using multiple lines for I/O, some devices increase the transfer rate by using double data rate transmission.[21][22]

Intel Enhanced Serial Peripheral Interface Bus[edit]

Intel has developed a successor to its Low Pin Count (LPC) bus that it calls the Enhanced Serial Peripheral Interface Bus, or eSPI for short. Intel aims to allow the reduction in the number of pins required on motherboards compared to systems using LPC, have more available throughput than LPC, reduce the working voltage to 1.8 volts to facilitate smaller chip manufacturing processes, allow eSPI peripherals to share SPI flash devices with the host (the LPC bus did not allow firmware hubs to be used by LPC peripherals), tunnel previous out-of-band pins through the eSPI bus, and allow system designers to trade off cost and performance.[23][24]

The eSPI bus can either be shared with SPI devices to save pins or be separate from the SPI bus to allow more performance, especially when eSPI devices need to use SPI flash devices.[23]

This standard defines an Alert# signal that is used by an eSPI slave to request service from the master. In a performance-oriented design or a design with only one eSPI slave, each eSPI slave will have its Alert# pin connected to an Alert# pin on the eSPI master that is dedicated to each slave, allowing the eSPI master to grant low-latency service because the eSPI master will know which eSPI slave needs service and will not need to poll all of the slaves to determine which device needs service. In a budget design with more than one eSPI slave, all of the Alert# pins of the slaves are connected to one Alert# pin on the eSPI master in a wired-OR connection, which will require the master to poll all the slaves to determine which ones need service when the Alert# signal is pulled low by one or more peripherals that need service. Only after all of the devices are serviced will the Alert# signal be pulled high due to none of the eSPI slaves needing service and therefore pulling the Alert# signal low.[23]

This standard allows designers to use 1-bit, 2-bit, or 4-bit communications at speeds from 20 to 66 MHz to further allow designers to trade off performance and cost.[23]

All communications that were out-of-band of the LPC bus like general-purpose input/output (GPIO) and System Management Bus (SMBus) are tunnelled through the eSPI bus via virtual wire cycles and out-of-band message cycles respectively in order to remove those pins from motherboard designs using eSPI.[23]

This standard supports standard memory cycles with lengths of 1 byte to 4 kilobytes of data, short memory cycles with lengths of 1, 2, or 4 bytes that have much less overhead compared to standard memory cycles, and I/O cycles with lengths of 1, 2, or 4 bytes of data which are low overhead as well. This significantly reduces overhead compared to the LPC bus, where all cycles except for the 128-byte firmware hub read cycle spends more than one half of all of the bus's throughput and time in overhead. The standard memory cycle allows a length of anywhere from 1 byte to 4 kilobytes in order to allow its larger overhead to be amortised over a large transaction. eSPI slaves are allowed to initiate bus master versions of all of the memory cycles. Bus master I/O cycles, which were introduced by the LPC bus specification, and ISA-style DMA including the 32-bit variant introduced by the LPC bus specification, are not present in eSPI. Therefore, bus master memory cycles are the only allowed DMA in this standard.[23]

eSPI slaves are allowed to use the eSPI master as a proxy to perform flash operations on a standard SPI flash memory slave on behalf of the requesting eSPI slave.[23]

64-bit memory addressing is also added, but is only permitted when there is no equivalent 32-bit address.[23]

The Intel Z170 chipset can be configured to implement either this bus or a variant of the LPC bus that is missing its ISA-style DMA capability and is underclocked to 24 MHz instead of the standard 33 MHz.[25]

See also[edit]


  1. ^ "What is Serial Synchronous Interface (SSI)?". Retrieved 2015-01-28. 
  2. ^ a b For slave devices
  3. ^ SPI Block Guide v3.06; Motorola/Freescale/NXP; 2003.
  4. ^ "Better SPI Bus Design in 3 Steps". dorkbot pdx. Retrieved 3 September 2015. 
  5. ^ Maxim-IC application note 3947: "Daisy-Chaining SPI Devices"
  6. ^ a b Not to be confused with the SDIO line of the half duplex implementation of the SPI bus, sometimes also called "3-wire SPI-bus". Here e.g. MOSI (via a resistor) and MISO (no resistor) of a master is connected to the SDIO line of a slave.
  7. ^ AVR910 - In-system programming
  8. ^ IEEE 1149.1-2013
  9. ^
  10. ^ SPI Adapter with support of custom serial protocols, Byte Paradigm.
  11. ^ "N5391B". 
  12. ^ Queued Serial Module Reference Manual, Freescale Semiconductor
  13. ^ Such as with the MultiChannel Serial Port Interface, or McSPI, used in Texas Instruments OMAP chips.
  14. ^ Such as the SPI controller on Atmel AT91 chips like the at91sam9G20, which is much simpler than TI's McSPI.
  15. ^ MICROWIRE Serial Interface National Semiconductor Application Note AN-452
  16. ^ MICROWIRE/PLUS Serial Interface for COP800 Family National Semiconductor Application Note AN-579
  17. ^ a b "W25Q16JV 3V 16M-bit serial flash memory sith dual/quad SPI" (PDF) (data sheet). Revision D. Winbond. 12 August 2016. Retrieved 2017-02-10. 
  18. ^ a b c "D25LQ64 1.8V Uniform Sector Dual and Quad SPI Flash" (PDF) (data sheet). version 0.1. GigaDevice. 11 February 2011. Retrieved 2017-02-10. 
  19. ^ "QuadSPI flash: Quad SPI mode vs. QPI mode". NXP community forums. December 2014. Retrieved 2016-02-10. 
  20. ^ "SST26VF032B / SST26VF032BA 2.5V/3.0V 32 Mbit Serial Quad I/O (SQI) Flash Memory" (PDF) (Data sheet). version E. Microchip, Inc. 2017. Retrieved 2017-02-10. 
  21. ^ Patterson, David (May 2012). "Quad Serial Peripheral Interface (QuadSPI) Module Updates" (PDF) (Application note). Freescale Semiconductor. Retrieved September 21, 2016. 
  22. ^ Pell, Rich (13 October 2011). "Improving performance using SPI-DDR NOR flash memory". EDN. 
  23. ^ a b c d e f g h Enhanced Serial Peripheral Interface (eSPI) Interface Base Specification (for Client and Server Platforms) (PDF) (Report). Revision 1.0. Intel. January 2016. Document number 327432-004. Retrieved 2017-02-05. 
  24. ^ Enhanced Serial Peripheral Interface (eSPI) Interface Specification (for Client Platforms) (PDF) (Report). Revision 0.6. Intel. May 2012. Document Number 327432-001EN. Retrieved 2017-02-05. 
  25. ^ "Intel® 100 Series Chipset Family PCH Datasheet, Vol. 1" (PDF). Retrieved April 15, 2015. 

External links[edit]