Delta-sigma modulation

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Delta-sigma (ΔΣ; or sigma-delta, ΣΔ) modulation is a method for encoding analog signals into digital signals as found in an analog-to-digital converter (ADC). It is also used to convert high bit-count, low-frequency digital signals into lower bit-count, higher-frequency digital signals as part of the process to convert digital signals into analog as part of a digital-to-analog converter (DAC).

In a conventional ADC, an analog signal is sampled with a sampling frequency and subsequently quantized in a multi-level quantizer into a digital signal. This process introduces quantization error noise. The first step in a delta-sigma modulation is delta modulation. In delta modulation the change in the signal (its delta) is encoded, rather than the absolute value. The result is a stream of pulses, as opposed to a stream of numbers as is the case with pulse code modulation (PCM). In delta-sigma modulation, accuracy of the modulation is improved by passing the digital output through a 1-bit DAC and adding (sigma) the resulting analog signal to the input signal (the signal before delta modulation), thereby reducing the error introduced by the delta-modulation.

Both ADCs and DACs can employ delta-sigma modulation. A delta-sigma ADC first encodes an analog signal using high-frequency delta-sigma modulation, and then applies a digital filter to form a higher-resolution but lower sample-frequency digital output. A delta-sigma DAC encodes a high-resolution digital input signal into a lower-resolution but higher sample-frequency signal that is mapped to voltages, and then smoothed with an analog filter. In both cases, the temporary use of a lower-resolution signal simplifies circuit design and improves efficiency.

Primarily because of its cost efficiency and reduced circuit complexity, this technique has found increasing use in modern electronic components such as DACs, ADCs, frequency synthesizers, switched-mode power supplies and motor controllers.[1] The coarsely-quantized output of a delta-sigma modulator is occasionally used directly in signal processing or as a representation for signal storage. For example, the Super Audio CD (SACD) stores the output of a delta-sigma modulator directly on a disk.


Why convert an analog signal into a stream of pulses?[edit]

In brief, because it is very easy to regenerate pulses at the receiver into the ideal form transmitted. The only part of the transmitted waveform required at the receiver is the sequence of binary pulse values. Given this sequence of bits, the transmitted waveform can be reconstructed electronically with great precision. In contrast, without conversion to a pulse stream but simply transmitting the analog signal directly, all noise in the system is added to the analog signal, permanently reducing its quality.

Why delta-sigma modulation?[edit]

Delta-sigma modulation converts the analog voltage into a pulse frequency or density and can be understood as pulse-density modulation or pulse-frequency modulation depending on implementation. In general, frequency may vary smoothly in infinitesimal steps, as may voltage, and both may serve as an analog of an infinitesimally varying physical variable such as acoustic pressure, light intensity, etc. The substitution of frequency for voltage is thus entirely natural and carries in its train the transmission advantages of a pulse stream.

Analog to digital conversion[edit]


The ADC generates a pulse stream in which the frequency, , of pulses in the stream is proportional to the analog voltage input, , so that , where k is a constant for the particular implementation. The interval between pulses, , is determined by a feedback loop arranged so that . The action of the feedback loop is to monitor the integral of and when that integral has incremented by , which is indicated by the integral waveform crossing a threshold, then subtracting from the integral of so that the combined waveform sawtooths between and . At each step a pulse is added to the pulse stream.

A counter sums the number of pulses that occur in a predetermined period, so that the sum, , is . In a given implementation, is chosen so that a digital display of the count, , is a display of with a predetermined scaling factor. Because may take any designed value, it may be made large enough to give any desired resolution or accuracy.


Fig. 1: Block diagram and waveforms for a sigma-delta ADC
Fig. 1a: Effect of clocking impulses

For the purpose of introduction, Fig. 1 illustrates the concept of delta-sigma modulation in its simplest asynchronous, unclocked form. Shown below that are waveforms at points designated by numbers 1 to 5 for an input of 0.2 volts in the left column and 0.4 volts in the right column.

The stream of delta impulses generated at each threshold crossing is shown at (2) and the difference between (1) and (2) is shown at (3). This difference is integrated to produce the waveform (4). The threshold detector generates a pulse (5) which starts as the waveform (4) crosses the threshold and is sustained until the waveform (4) falls below the threshold. The threshold (5) triggers the impulse generator to produce a fixed strength impulse.

The integral (4) crosses the threshold in half the time in the right column than in the left column. Thus the frequency of impulses is doubled. Hence the count increments at twice the speed on the right to that on the left; this is consistent with the input voltage being doubled.

Construction of the waveforms illustrated at (4) is aided by concepts associated with the Dirac delta function in that, by definition, all impulses of the same strength produce the same step when integrated. Then (4) is constructed using an intermediate step (6) in which each integrated impulse is represented by a step of the assigned strength which decays to zero at the rate determined by the input voltage. The effect of the finite duration of the impulse is constructed in (4) by drawing a line from the base of the impulse step at zero volts to intersect the decay line from (6) at the full duration of the impulse.

Now consider the circuit outside the loop. The summing interval is a prefixed time and at its expiry the count is stored the buffer and the counter reset. The buffer then presents a sequence of digital values corresponding to the analog signal level.

If the ratio between the impulse interval and the summing interval is equal to the maximum (full scale) count, it is then possible for the impulse duration and the summing interval to be defined by the same clock with a suitable arrangement of logic and counters. This has the advantage that neither interval has to be defined with absolute precision as only the ratio is important. Then to achieve overall accuracy it is only necessary that the amplitude of the impulse be accurately defined.

Implementations may further constrain operation of the impulse generator such that the start of the impulse is delayed until the next occurrence of the appropriate clock pulse boundary. The effect of this delay is illustrated in Fig. 1a for a sequence of impulses which occur at a nominal 2.5 clock intervals. The effect is that the maximum error that can occur due to clocking is marginally less than one count.

Practical implementation[edit]

Fig. 1b: circuit diagram
Fig. 1c: ADC waveforms

A circuit diagram for a practical implementation is illustrated in Fig. 1b and the associated waveforms in Fig. 1c. The scrap view of an alternative front end shown in Fig. 1b has the advantage that the voltage at the switch terminals are relatively constant and close to 0.0 V. Also the current generated through R by −Vref is constant at −Vref/R so that much less noise is radiated to adjacent parts of the circuit. This would be the preferred front end in practice but, in order to show the impulse as a voltage pulse so as to be consistent with previous discussion, the front end given here, which is a functional equivalent, is used.

The waveforms shown in Fig. 1c are unusually complex because they are intended to illustrate the loop behaviour under extreme conditions, Vin saturated on at full scale, 1.0V, and saturated off at zero. The intermediate state is also indicated, Vin at 0.4V, and is the usual operating condition between 0 and 1.0v where it is very similar to the operation of the illustrative block diagram, Fig. 1.

From the top of Fig 1c the waveforms, labelled as they are on the circuit diagram, are:

The clock
(a) Vin. This is shown as varying from 0.4 V initially to 1.0 V and then to zero volts to show the effect on the feedback loop.
(b) The impulse waveform feeding the integrator. Controlled by flip flop output (f) below.
(c) The current into the capacitor, Ic, is the linear sum of the impulse voltage upon R and Vin upon R. To show this sum as a voltage the product R × Ic is plotted. The input impedance of the amplifier is regarded as so high that the current drawn by the input is neglected. The capacitor is connected between the negative input terminal of the amplifier and its output terminal. With this connection it provides a negative feedback path around the amplifier. The input voltage change is equal to the output voltage change divided by the amplifier gain. With very high amplifier gain the change in input voltage can be neglected and so the input voltage is held close to the voltage on the positive input terminal which in this case is held at 0V. Because the voltage at the input terminal is 0V the voltage across R is simply Vin so that the current into the capacitor is the input voltage divided by the resistance of R.
(d) The negated integral of Ic. This negation is standard for the op amp integrator and comes about because the current into the capacitor at the amplifier input is the current out of the capacitor at the amplifier output and the voltage is the integral of the current divided by the capacitance of C.
(e) The comparator output. The comparator is a very high gain amplifier with its plus input terminal connected for reference to 0.0 V. Whenever the negative input terminal is taken negative with respect the positive terminal of the amplifier the output saturates positive and conversely negative saturation for positive input. Thus the output saturates positive whenever the integral (d) goes below the 0 V reference level and the output remains there until (d) goes positive with respect to the 0 V reference.
(f) The impulse timer is a D type positive edge triggered flip flop. Input information applied at D is transferred to Q on the occurrence of the positive edge of the clock pulse. Thus when the comparator output (e) is positive, Q goes positive or remains positive at the next positive clock edge. Similarly, when (e) is negative Q goes negative at the next positive clock edge. Q controls the electronic switch to generate the current impulse (b) into the integrator. Examination of the waveform (e) during the initial period illustrated, when Vin is 0.4 V, shows (e) crossing the threshold well before the positive edge of the clock pulse so that there is an appreciable delay before the impulse starts. After the start of the impulse there is further delay while (d) climbs back past the threshold. During this time the comparator output (e) remains high but goes low before the next trigger edge at which point the impulse timer goes low to follow the comparator. Thus the clock, in part, determines the duration of the impulse. For the next impulse the threshold is crossed immediately before the trigger edge and so the comparator is only briefly positive. Vin (a) then goes to full scale, +Vref, shortly before the end of the next impulse. For the remainder of that impulse the capacitor current (c) goes to zero and hence the integrator slope briefly goes to zero. Following this impulse, the full scale positive current flows (c) and the integrator sinks at its maximum rate and so crosses the threshold well before the next trigger edge. At that edge the impulse starts and the Vin current is now matched by the reference current so that the net capacitor current (c) is zero. The integration now has zero slope and remains at the negative value it had at the start of the impulse. This has the effect that the impulse current remains switched on because Q is stuck positive because the comparator is stuck positive at every trigger edge. This is consistent with contiguous, butting impulses which is representative of full scale input. Next Vin (a) goes to zero which causes the current sum (c) to go fully negative and the integral ramps up. It shortly thereafter crosses the threshold and this in turn is followed by Q, thus switching the impulse current off. The capacitor current (c) is now zero and so the integral slope is zero, remaining constant at the value it had acquired at the end of the impulse.
(g) The countstream is generated by gating the negated clock with Q to produce this waveform. Thereafter the summing interval, sigma count and buffered count are produced using appropriate counters and registers.

Improvements to Resolution and Noise[edit]

Examination of Fig.1c(g) shows that there are zero pulses in the countstream when the input voltage is zero. This has no consequence when the application is an analogue to digital converter but when the application is a modulator the effect is that high frequency components of a complex signal are not resolved which might be critical. This effect is known as Intermodulation Distortion (IMD). One of the pitfalls of applying linear analysis to a non-linear system is that IMD, because it can be a consequence of non-linearity, is not present in the analysis. Purely for illustrative purposes a method to mitigate this would be to add an 0.5 volt constant bias to the input voltage so the it now can swing +/- 0.5v about the bias.This still has zero pulses in the countstream when the input is -0.5V. Then we must limit the input swing to +/- 0.4v say so that the minimum countstream frequency is greater than zero. We can choose the clock frequency so that the minimum countstream frequency at -0.4V is greater than the Nyquist limit so that even the highest input frequency component is resolved.We can increase the clock frequency still higher until a low pass filter sufficiently removes the pulsations while fully recovering the input signal. In this illustrative discussion the filtered signal will also recover the bias which can be removed by an analogue adder while still retaining the DC component of the input signal.

In the case of an asynchronous system the above advantages can be achieved by applying the 0.5V input bias, limiting the input swing to +/- 0.4v as mentioned above, choosing a very short impulse and having a low integrator RC time constant. This also avoids the noise due to clocking.


According to WOOLEY [2] the seminal paper combining feedback with oversampling to achieve delta modulation was by F de Jager in 1952. The Delta-Sigma configuration was devised by INOSE et al. in 1962 to solve problems in the accurate transmission of analog signals.[3] In that application it was the pulse stream that was transmitted and the original analog signal recovered with a low pass filter after the received pulses had been reformed. This low pass filter performed the summation function associated with Σ. The highly mathematical treatment of transmission errors was introduced by them and is appropriate when applied to the pulse stream but these errors are lost in the accumulation process associated with Σ.

Frequency domain analysis shows that the incoming waveform can be represented over the summing interval by the sum of a constant plus a fundamental and harmonics each of which has an exact integer number of cycles over the sampling period. The integral of a sine wave over one or more full cycles is zero. Therefore, the integral of the incoming waveform over the summing interval reduces to the constant, the mean over the interval. The interval between pulses is proportional to the inverse of the mean of the input voltage during that interval and thus over that interval, ts, is a sample of the mean of the input voltage proportional to V/ts. Thus the average of the input voltage over the summing period is VΣ/N and is the mean of means and so subject to little variance.

The effect of constraining a pulse to only occur on clock boundaries is to introduce noise. The noise is generated by waiting for the next clock boundary. This will have its most deleterious effect on the high-frequency components of a complex signal. Clocking in the ADC environment can be beneficial because it removes one source of error, namely the ratio between the impulse duration and the summing interval. Clocking may serve no useful purpose in a single channel transmission environment since it is a source of both noise and complexity. It is potentially useful in a time division multiplex transmission environment.

Digital to analog conversion[edit]

Delta-sigma modulators are often used in digital to analog converters (DACs). In general, a DAC converts a digital number representing some analog value into that analog value. For example, the analog voltage level feeding a speaker may be represented as a 20-bit digital number; the DAC converts that number into the desired voltage.

Each pulse of the pulse stream has a known, constant amplitude and duration , and thus has a known integral but variable separating interval. In a formal analysis, an impulse such as integral is treated as the Dirac delta function (δ function) and is specified by the step produced on integration. Here we indicate that step as .

Between impulses, the slope of the integral is proportional to , that is, for some it equals . Whence .

The resulting two-level signal is now like the desired signal, but with higher frequency components associated with the high-speed transitions between the two levels. These added frequency components can be filtered away by a simple low-pass filter. The result is a reproduction of the original, desired analog signal from the digital values.

To actually drive a load (like a speaker) a DAC is usually connected to or integrated with an electronic amplifier. This can be done using a delta-sigma modulator in a Class D Amplifier. In this case, a multi-bit digital number is input to the delta-sigma modulator, which converts it into a faster sequence of 0s and 1s. These 0s and 1s are then converted into analog voltages. The conversion, usually with MOSFET drivers, is very efficient in terms of power because the drivers are usually either fully on or fully off, and in these states have low power loss.

The circuit itself is relatively small and inexpensive, and the MOSFETs used for the power amplification are simple. This is in contrast to a multi-bit DAC which can have very stringent design conditions to precisely represent digital values with a large number of bits. The use of a delta-sigma modulator in digital-to-analog conversion has enabled a cost-effective, low power, and high performance solution.

Relationship to delta modulation[edit]

Fig. 2: Derivation of delta-sigma from delta modulation

Delta-sigma modulation is inspired by delta modulation, as shown in Fig. 2. If quantization were homogeneous (e.g., if it were linear), the following would be a sufficient derivation of the equivalence:

  1. Start with a block diagram of a delta modulator/demodulator.
  2. The linearity property of integration () makes it possible to move the integrator, which reconstructs the analog signal in the demodulator section, in front of the delta modulator.
  3. Again, the linearity property of the integration allows the two integrators to be combined and a delta-sigma modulator/demodulator block diagram is obtained.

However, the quantizer is not homogeneous, and so this explanation is flawed. It's true that delta-sigma is inspired by delta modulation, but the two are distinct in operation. From the first block diagram in Fig. 2, the integrator in the feedback path can be removed if the feedback is taken directly from the input of the low-pass filter. Hence, for delta modulation of input signal , the low-pass filter sees the signal

However, sigma-delta modulation of the same input signal places at the low-pass filter

In other words, delta-sigma and delta modulation swap the position of the integrator and quantizer. The net effect is a simpler implementation that has the added benefit of shaping the quantization noise away from signals of interest (i.e., signals of interest are low-pass filtered while quantization noise is high-pass filtered). This effect becomes more dramatic with increased oversampling, which allows for quantization noise to be somewhat programmable. On the other hand, delta modulation shapes both noise and signal equally.

Additionally, the quantizer (e.g., comparator) used in delta modulation has a small output representing a small step up and down the quantized approximation of the input while the quantizer used in delta-sigma must take values outside of the range of the input signal, as shown in Fig. 3.

Fig. 3: An example of SDM of 100 samples of one period a sine wave. 1-bit samples (e.g., comparator output) overlaid with sine wave where logic high (e.g., ) represented by blue and logic low (e.g., ) represented by white.

In general, delta-sigma has some advantages versus delta modulation:

  • The whole structure is simpler:
    • Only one integrator is needed
    • The demodulator can be a simple linear filter (e.g., RC or LC filter) to reconstruct the signal
    • The quantizer (e.g., comparator) can have full-scale outputs
  • The quantized value is the integral of the difference signal, which makes it less sensitive to the rate of change of the signal.


The principle of the ΔΣ architecture is explained at length in section 2. Initially, when a sequence starts, the circuit will have an arbitrary state which is dependent on the integral of all previous history. In mathematical terms this corresponds to the arbitrary integration constant of the indefinite integral. This follows from the fact that at the heart of the method there is an integrator which can have any arbitrary state dependent on previous input, see Fig. 1c (d). From the occurrence of the first pulse onward the frequency of the pulse stream is proportional to the input voltage to be transformed. A demonstration applet is available online to simulate the whole architecture.[4]


There are many kinds of ADC that use this delta-sigma structure. The above analysis focuses on the simplest 1st-order, 2-level, uniform-decimation sigma-delta ADC. Many ADCs use a second-order 5-level sinc3 sigma-delta structure.

Second-order and higher-order modulator[edit]

Fig. 4: Block diagram of a second-order ΔΣ modulator

The number of integrators, and consequently, the numbers of feedback loops, indicates the order of a ΔΣ-modulator; a second-order ΔΣ modulator is shown in Fig. 4. First-order modulators are unconditionally stable, but stability analysis must be performed for higher-order modulators.

3-level and higher quantizer[edit]

The modulator can also be classified by the number of bits it has in its output, which strictly depends on the output of the quantizer. The quantizer can be realized with a N-level comparator, thus the modulator has log2N-bit output. A simple comparator has 2 levels and so is 1 bit quantizer; a 3-level quantizer is called a "1.5" bit quantizer; a 4-level quantizer is a 2 bit quantizer; a 5-level quantizer is called a "2.5 bit" quantizer.[5]

Decimation structures[edit]

The conceptually simplest decimation structure is a counter that is reset to zero at the beginning of each integration period, then read out at the end of the integration period.

The multi-stage noise shaping (MASH) structure has a noise shaping property, and is commonly used in digital audio and fractional-N frequency synthesizers. It comprises two or more cascaded overflowing accumulators, each of which is equivalent to a first-order sigma-delta modulator. The carry outputs are combined through summations and delays to produce a binary output, the width of which depends on the number of stages (order) of the MASH. Besides its noise shaping function, it has two more attractive properties:

  • simple to implement in hardware; only common digital blocks such as accumulators, adders, and D flip-flops are required
  • unconditionally stable (there are no feedback loops outside the accumulators)

A very popular decimation structure is the sinc filter. For second-order modulators, the sinc3 filter is close to optimum.[6][7]

Quantization theory formulas[edit]

When a signal is quantized, the resulting signal approximately has the second-order statistics of a signal with independent additive white noise. Assuming that the signal value is in the range of one step of the quantized value with an equal distribution, the root mean square value of this quantization noise is

In reality, the quantization noise is of course not independent of the signal; this dependence is the source of idle tones and pattern noise in Sigma-Delta converters.

The over-sampling ratio (OSR), where is the sampling frequency and is Nyquist rate, is defined by

The RMS noise voltage within the band of interest can be expressed in terms of OSR


Fig. 5: Noise shaping curves and noise spectrum in ΔΣ modulator

Let's consider a signal at frequency and a sampling frequency of much higher than Nyquist rate (see fig. 5). ΔΣ modulation is based on the technique of oversampling to reduce the noise in the band of interest (green), which also avoids the use of high-precision analog circuits for the anti-aliasing filter. The quantization noise is the same both in a Nyquist converter (in yellow) and in an oversampling converter (in blue), but it is distributed over a larger spectrum. In ΔΣ-converters, noise is further reduced at low frequencies, which is the band where the signal of interest is, and it is increased at the higher frequencies, where it can be filtered. This technique is known as noise shaping.

For a first-order delta-sigma modulator, the noise is shaped by a filter with transfer function . Assuming that the sampling frequency , the quantization noise in the desired signal bandwidth can be approximated as:


Similarly for a second-order delta-sigma modulator, the noise is shaped by a filter with transfer function . The in-band quantization noise can be approximated as:


In general, for a -order ΔΣ-modulator, the variance of the in-band quantization noise:


When the sampling frequency is doubled, the signal to quantization noise is improved by for a -order ΔΣ-modulator. The higher the oversampling ratio, the higher the signal-to-noise ratio and the higher the resolution in bits.

Another key aspect given by oversampling is the speed/resolution tradeoff. In fact, the decimation filter put after the modulator not only filters the whole sampled signal in the band of interest (cutting the noise at higher frequencies), but also reduces the frequency of the signal increasing its resolution. This is obtained by a sort of averaging of the higher data rate bitstream.

Example of decimation[edit]

Let's have, for instance, an 8:1 decimation filter and a 1-bit bitstream; if we have an input stream like 10010110, counting the number of ones, we get 4. Then the decimation result is 4/8 = 0.5. We can then represent it with a 3-bits number 100 (binary), which means half of the largest possible number. In other words,

  • the sample frequency is reduced by a factor of eight
  • the serial (1-bit) input bus becomes a parallel (3-bits) output bus.


The technique was first presented in the early 1960s by professor Haruhiko Yasuda while he was a student at Waseda University, Tokyo, Japan.[citation needed] The name Delta-Sigma comes directly from the presence of a Delta modulator and an integrator, as firstly introduced by Inose et al. in their patent application.[3] That is, the name comes from integrating or "summing" differences, which are operations usually associated with Greek letters Sigma and Delta respectively. Both names Sigma-Delta and Delta-Sigma are frequently used.

See also[edit]


  1. ^ Sangil Park, Principles of Sigma-Delta Modulation for Analog-to-Digital Converters (PDF), Motorola, retrieved 2017-09-01
  2. ^ "The Evolution of Oversampling Analog-to-Digital Converters" Bruce A. Wooley
  3. ^ a b H. Inose, Y. Yasuda, J. Murakami, "A Telemetering System by Code Manipulation -- ΔΣ Modulation", IRE Trans on Space Electronics and Telemetry, Sep. 1962, pp. 204-209.
  4. ^ "Sigma-Delta ADC Tutorial - Design Center - Analog Devices".
  5. ^ Sigma-delta class-D amplifier and control method for a sigma-delta class-D amplifier by Jwin-Yen Guo and Teng-Hung Chang
  6. ^ A Novel Architecture for DAQ in Multi-channel, Large Volume, Long Drift Liquid Argon TPC by S. Centro, G. Meng, F. Pietropaola, S. Ventura 2006
  7. ^ A Low Power Sinc3 Filter for ΣΔ Modulators by A. Lombardi, E. Bonizzoni, P. Malcovati, F. Maloberti 2007

External links[edit]