Silicon on insulator
Silicon on insulator (SOI) technology refers to the use of a layered silicon–insulator–silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance, thereby improving performance. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or sapphire (these types of devices are called silicon on sapphire, or SOS). The choice of insulator depends largely on intended application, with sapphire being used for high-performance radio frequency (RF) and radiation-sensitive applications, and silicon dioxide for diminished short channel effects in microelectronics devices. The insulating layer and topmost silicon layer also vary widely with application.
The implementation of SOI technology is one of several manufacturing strategies employed to allow the continued miniaturization of microelectronic devices, colloquially referred to as "extending Moore's Law" (or "More Moore", abbreviated "MM"). Reported benefits of SOI technology relative to conventional silicon (bulk CMOS) processing include:
- Lower parasitic capacitance due to isolation from the bulk silicon, which improves power consumption at matched performance.
- Resistance to latchup due to complete isolation of the n- and p-well structures.
- Higher performance at equivalent VDD. Can work at low VDD's.
- Reduced temperature dependency due to no doping.
- Better yield due to high density, better wafer utilization.
- Reduced antenna issues
- No body or well taps are needed.
- Lower leakage currents due to isolation thus higher power efficiency.
- Inherently radiation hardened ( resistant to soft errors ), thus reducing the need for redundancy.
From a manufacturing perspective, SOI substrates are compatible with most conventional fabrication processes. In general, an SOI-based process may be implemented without special equipment or significant retooling of an existing factory. Among challenges unique to SOI are novel metrology requirements to account for the buried oxide layer and concerns about differential stress in the topmost silicon layer. The threshold voltage of the transistor depends on the history of operation and applied voltage to it, thus making modeling harder. The primary barrier to SOI implementation is the drastic increase in substrate cost, which contributes an estimated 10–15% increase to total manufacturing costs.
An SOI MOSFET is a semiconductor device (MOSFET) in which a semiconductor layer such as silicon or germanium is formed on an insulator layer which may be a buried oxide (BOX) layer formed in a semiconductor substrate. SOI MOSFET devices are adapted for use by the computer industry. The buried oxide layer can be used in SRAM designs. There are two type of SOI devices: PDSOI (partially depleted SOI) and FDSOI (fully depleted SOI) MOSFETs. For an n-type PDSOI MOSFET the sandwiched p-type film between the gate oxide (GOX) and buried oxide (BOX) is large, so the depletion region can't cover the whole p region. So to some extent PDSOI behaves like bulk MOSFET. Obviously there are some advantages over the bulk MOSFETs. The film is very thin in FDSOI devices so that the depletion region covers the whole film. In FDSOI the front gate (GOX) supports less depletion charges than the bulk so an increase in inversion charges occurs resulting in higher switching speeds. The limitation of the depletion charge by the BOX induces a suppression of the depletion capacitance and therefore a substantial reduction of the subthreshold swing allowing FD SOI MOSFETs to work at lower gate bias resulting in lower power operation. The subthreshold swing can reach the minimum theoretical value for MOSFET at 300K, which is 60mV/decade. This ideal value was first demonstrated using numerical simulation [] []. Other drawbacks in bulk MOSFETs, like threshold voltage roll off, etc. are reduced in FDSOI since the source and drain electric fields can't interfere due to the BOX. The main problem in PDSOI is the "floating body effect (FBE)" since the film is not connected to any of the supplies.
Manufacture of SOI wafers
SiO2-based SOI wafers can be produced by several methods:
- SIMOX - Separation by IMplantation of OXygen – uses an oxygen ion beam implantation process followed by high temperature annealing to create a buried SiO2 layer.
- Wafer bonding – the insulating layer is formed by directly bonding oxidized silicon with a second substrate. The majority of the second substrate is subsequently removed, the remnants forming the topmost Si layer.
- One prominent example of a wafer bonding process is the Smart Cut method developed by the French firm Soitec which uses ion implantation followed by controlled exfoliation to determine the thickness of the uppermost silicon layer.
- NanoCleave is a technology developed by Silicon Genesis Corporation that separates the silicon via stress at the interface of silicon and silicon-germanium alloy.
- ELTRAN is a technology developed by Canon which is based on porous silicon and water cut.
- Seed methods - wherein the topmost Si layer is grown directly on the insulator. Seed methods require some sort of template for homoepitaxy, which may be achieved by chemical treatment of the insulator, an appropriately oriented crystalline insulator, or vias through the insulator from the underlying substrate.
An exhaustive review of these various manufacturing processes may be found in reference
Use in the microelectronics industry
IBM began to use SOI in the high-end RS64-IV "Istar" PowerPC-AS microprocessor in 2000. Other examples of microprocessors built on SOI technology include AMD's 130 nm, 90 nm, 65 nm, 45 nm and 32 nm single, dual, quad, six and eight core processors since 2001. Freescale adopted SOI in their PowerPC 7455 CPU in late 2001, currently Freescale is shipping SOI products in 180 nm, 130 nm, 90 nm and 45 nm lines. The 90 nm Power Architecture based processors used in the Xbox 360, PlayStation 3 and Wii use SOI technology as well. Competitive offerings from Intel however continues to use conventional bulk CMOS technology for each process node, instead focusing on other venues such as HKMG and Tri-gate transistors to improve transistor performance. In January 2005, Intel researchers reported on an experimental single-chip silicon rib waveguide Raman laser built using SOI.
Use in high-performance radio frequency (RF) applications
In 1990, Peregrine Semiconductor began development of an SOI process technology utilizing a standard 0.5 μm CMOS node and an enhanced sapphire substrate. Its patented silicon on sapphire (SOS) process is widely used in high-performance RF applications. The intrinsic benefits of the insulating sapphire substrate allow for high isolation, high linearity and electro-static discharge (ESD) tolerance. Multiple other companies have also applied SOI technology to successful RF applications in smartphones and cellular radios.
Use in photonics
SOI wafers are widely used in silicon photonics. The crystalline silicon layer on insulator can be used to fabricate optical waveguides and other passive optical devices for integrated optics. The crystalline silicon layer is sandwiched between the buried insulator (Silicon oxide, Sapphire etc.) and top cladding of air (or Silicon oxide or any other low refractive index material). This enables propagation of electromagnetic waves in the waveguides on the basis of total internal reflection.
- Strain engineering
- Intel TeraHertz - similar technology from Intel.
- Wafer (electronics)
- Wafer bonding
- Silicon on sapphire
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- Marshall, Andrew; Natarajan, Sreedhar (2002). SOI design: analog, memory and digital techniques. Boston: Kluwer. ISBN 0792376404.
- Colinge, Jean-Pierre (1991). Silicon-on-Insulator Technology: Materials to VLSI. Berlin: Springer Verlag. ISBN 978-0-7923-9150-0.
- Silicon-on-insulator - SOI technology and ecosystem - Emerging SOI applications by Horacio Mendez, Executive Director of the SOI Industry Consortium, April 9, 2009
- IBM touts chipmaking technology
- United States Patent 6,835,633 SOI wafers with 30-100 Ang. Buried OX created by wafer bonding using 30-100 Ang. thin oxide as bonding layer
- United States Patent 7,002,214 Ultra-thin body super-steep retrograde well (SSRW) FET devices
- Ultrathin-body SOI MOSFET for deep-sub-tenth micron era; Yang-Kyu Choi; Asano, K.; Lindert, N.; Subramanian, V.; Tsu-Jae King; Bokor, J.; Chenming Hu; Electron Device Letters, IEEE; Volume 21, Issue 5, May 2000 Page(s):254 - 255
- United States Patent 7138685 " Vertical MOSFET SRAM cell" describes SOI buried oxide (BOX) structures and methods for implementing enhanced SOI BOX structures.
- F. Balestra, Characterization and Simulation of SOI MOSFETs with Back Potential Control, PhD thesis, INP-Grenoble, 1985
- F. Balestra, Challenges to Ultralow-Power Semiconductor Device Operation, in “Future Trends in Microelectronics-Journey into the unknown”, S. Lury, J. Xu, A. Zaslavsky Eds., J. Wiley & Sons, 2016
- U.S. Patent 5,888,297 Method of fabricating SOI substrate Atsushi Ogura, Issue date: Mar 30, 1999
- U.S. Patent 5,061,642 Method of manufacturing semiconductor on insulator Hiroshi Fujioka, Issue date: Oct 29, 1991
- SIMOX-SOI Technology: Ibis Technology
- "SemiConductor Wafer Bonding: Science and Technology" by Q.-Y. Tong & U. Gösele, Wiley-Interscience, 1998, ISBN 978-0-471-57481-1
- U.S. Patent 4,771,016 Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor, George Bajor et al., Issue date: Sep 13, 1988
- ELTRAN - Novel SOI Wafer Technology, JSAPI vol.4
- U.S. Patent 5,417,180
- Chip Architect: Intel and Motorola/AMD's 130 nm processes to be revealed
- Process Technology
- Rong, Haisheng; Liu, Ansheng; Jones, Richard; Cohen, Oded; Hak, Dani, Nicolaescu, Remus; Fang, Alexander; Paniccia, Mario (January 2005). "An all-silicon Raman laser" (PDF). Nature. 433: 292–294. doi:10.1038/nature03723.
- TSMC has no customer demand for SOI technology - Fabtech - The online information source for semiconductor professionals
- Chartered expands foundry market access to IBM's 90nm SOI technology
- Madden, Joe. "Handset RFFEs: MMPAs, Envelope Tracking, Antenna Tuning, FEMs, and MIMO" (PDF). Mobile Experts. Retrieved 2 May 2012.[dead link]
- "Silicon photonics: an introduction" by Graham T. Reed, Andrew P. Knights. WIley. Page 111
- SOI Industry Consortium - a site with extensive information and education for SOI technology
- SOI IP portal - A search engine for SOI IP
- AMDboard - a site with extensive information regarding SOI technology
- Advanced Substrate News - a newsletter about the SOI industry, produced by Soitec.
- MIGAS '04 - The 7th session of MIGAS International Summer School on Advanced Microelectronics, devoted to SOI technology and devices.
- MIGAS '09 - 12th session of the International Summer School on Advanced Microelectronics: "Silicon on Insulator (SOI) Nanodevices"