This article includes a list of general references, but it remains largely unverified because it lacks sufficient corresponding inline citations. (August 2009) (Learn how and when to remove this template message)
A single-event upset (SEU) is a change of state caused by one single ionizing particle (ions, electrons, photons...) striking a sensitive node in a micro-electronic device, such as in a microprocessor, semiconductor memory, or power transistors. The state change is a result of the free charge created by ionization in or close to an important node of a logic element (e.g. memory "bit"). The error in device output or operation caused as a result of the strike is called an SEU or a soft error.
The SEU itself is not considered permanently damaging to the transistor's or circuits' functionality unlike the case of single-event latch-up (SEL), single-event gate rupture (SEGR), or single-event burnout (SEB). These are all examples of a general class of radiation effects in electronic devices called single-event effects (SEEs).
Single-event upsets were first described during above-ground nuclear testing, from 1954 to 1957, when many anomalies were observed in electronic monitoring equipment. Further problems were observed in space electronics during the 1960s, although it was difficult to separate soft failures from other forms of interference. In 1972, a Hughes satellite experienced an upset where the communication with the satellite was lost for 96 seconds and then recaptured. Scientists Dr. Edward C. Smith, Al Holman, and Dr. Dan Binder explained the anomaly as a single-event upset (SEU) and published the first SEU paper in the IEEE Transactions on Nuclear Science journal in 1975. In 1978, the first evidence of soft errors from alpha particles in packaging materials was described by Timothy C. May and M.H. Woods. In 1979, James Ziegler of IBM, along with W. Lanford of Yale, first described the mechanism whereby a sea-level cosmic ray could cause a single event upset in electronics.
Terrestrial SEU arise due to cosmic particles colliding with atoms in the atmosphere, creating cascades or showers of neutrons and protons, which in turn may interact with electronic circuits. At deep sub-micron geometries, this affects semiconductor devices in the atmosphere.
In space, high-energy ionizing particles exist as part of the natural background, referred to as galactic cosmic rays (GCR). Solar particle events and high-energy protons trapped in the Earth's magnetosphere (Van Allen radiation belts) exacerbate this problem. The high energies associated with the phenomenon in the space particle environment generally render increased spacecraft shielding useless in terms of eliminating SEU and catastrophic single-event phenomena (e.g. destructive latch-up). Secondary atmospheric neutrons generated by cosmic rays can also have sufficiently high energy for producing SEUs in electronics on aircraft flights over the poles or at high altitude. Trace amounts of radioactive elements in chip packages also lead to SEUs.
Testing for SEU sensitivity
The sensitivity of a device to SEU can be empirically estimated by placing a test device in a particle stream at a cyclotron or other particle accelerator facility. This particular test methodology is especially useful for predicting the SER (soft error rate) in known space environments, but can be problematic for estimating terrestrial SER from neutrons. In this case, a large number of parts must be evaluated, possibly at different altitudes, to find the actual rate of upset.
Another way to empirically estimate SEU tolerance is to use a chamber shielded for radiation, with a known radiation source, such as Caesium-137.
When testing microprocessors for SEU, the software used to exercise the device must also be evaluated to determine which sections of the device were activated when SEUs occurred.
SEUs and circuit design
By definition, SEUs do not destroy the circuits involved, but they can cause errors. In space-based microprocessors, one of the most vulnerable portions is often the 1st and 2nd-level cache memories, because these must be very small and have very high-speed, which means that they do not hold much charge. Often these caches are disabled if terrestrial designs are being configured to survive SEUs. Another point of vulnerability is the state machine in the microprocessor control, because of the risk of entering "dead" states (with no exits), however, these circuits must drive the entire processor, so they have relatively large transistors to provide relatively large electric currents and are not as vulnerable as one might think. Another vulnerable processor component is the RAM. To ensure resilience to SEUs, often an error correcting memory is used, together with circuitry to periodically read (leading to correction) or scrub (if reading does not lead to correction) the memory of errors, before the errors overwhelm the error-correcting circuitry.
In digital and analog circuits, a single event may cause one or more voltages pulses (i.e. glitches) to propagate through the circuit, in which case it is referred to as a single-event transient (SET). Since the propagating pulse is not technically a change of "state" as in a memory SEU, one should differentiate between SET and SEU. If a SET propagates through digital circuitry and results in an incorrect value being latched in a sequential logic unit, it is then considered an SEU.
Hardware problems can also occur for related reasons. Under certain circumstances (of both circuit design, process design, and particle properties) a "parasitic" thyristor inherent to CMOS designs can be activated, effectively causing an apparent short-circuit from power to ground. This condition is referred to as latch-up, and in absence of constructional countermeasures, often destroys the device due to thermal runaway. Most manufacturers design to prevent latch-up, and test their products to ensure that latch-up does not occur from atmospheric particle strikes. In order to prevent latch-up in space, epitaxial substrates, silicon on insulator (SOI) or silicon on sapphire (SOS) are often used to further reduce or eliminate the susceptibility.
In the 2003 elections in Brussels's municipality Schaerbeek (Belgium), an anomalous recorded number of votes triggered an investigation that concluded a SEU was responsible for giving a candidate 4,096 extra votes.
- Radiation hardening
- Cosmic rays
- Hamming distance
- Parity bit
- Gray code
- Libaw-Craig code / Johnson code
- Johnson counter
- Neutron-Induced Single Event Upset (SEU) FAQ, Microsemi Corporation, retrieved October 7, 2018,
The cause has been traced to errors in an on-board computer suspected to have been induced by cosmic rays.
- Binder, Smith, Holman (1975). "Satellite Anomalies from Galactic Cosmic Rays". IEEE Transactions on Nuclear Science. NS-22, No. 6 (6): 2675–2680. doi:10.1109/TNS.1975.4328188 – via IEEE Explore.CS1 maint: multiple names: authors list (link)
- Mittal, Sparsh; Vetter, Jeffrey S. (2016). "A Survey of Techniques for Modeling and Improving Reliability of Computing Systems". IEEE Transactions on Parallel and Distributed Systems. 27 (4): 1226–1238. doi:10.1109/TPDS.2015.2426179. OSTI 1261262.
- Ian Johnston (17 February 2017). "Cosmic particles can change elections and cause planes to fall through the sky, scientists warn". Independent. Retrieved 5 September 2018.
- General SEU
- T.C. May and M.H. Woods, IEEE Trans Electron Devices ED-26, 2 (1979)
- www.seutest.com - Soft-error testing resources to support the JEDEC JESD89A test protocol.
- J. F. Ziegler and W. A. Lanford, "Effect of Cosmic Rays on Computer Memories", Science, 206, 776 (1979)
- Ziegler, et al. IBM Journal of Research and Development. Vol. 40, 1 (1996).
- NASA Introduction to SEU from Goddard Space Flight Center Radiation Effects Facility
- NASA/Smithsonian abstract search.
- "Estimating Rates of Single-Event Upsets", J. Zoutendyk, NASA Tech Brief, Vol. 12, No. 10, item #152, Nov. 1988.
- Boeing Radiation Effects Laboratory, focussed on Avionics
- A Memory Soft Error Measurement on Production Systems, 2007 USENIX Annual Technical Conference, pp. 275-280
- A Highly Reliable SEU Hardened Latch and High Performance SEU Hardened Flip-Flop, International Symposium on Quality Electronic Design (ISQED), California, USA, March 19--21, 2012
- SEU in programmable logic devices
- "Single-Event Upsets: Should I Worry?" Xilinx Corp.
- "Virtex-4: Soft Errors Reduced by Nearly Half!" A. Lesea, Xilinx TecXclusive, 6 May 2005.
- Single Event Upsets Altera Corp.
- Evaluation of LSI Soft Errors Induced by Terrestrial Cosmic rays and Alpha Particles - H. Kobayashi, K. Shiraishi, H. Tsuchiya, H. Usuki (all of Sony), and Y. Nagai, K. Takahisa (Osaka University), 2001.
- SEU-Induced Persistent Error Propagation in FPGAs K. Morgan (Brigham Young University), Aug. 2006.
- Microsemi neutron immune FPGA technology.
- SEU in microprocessors
- Elder, J.H.; Osborn, J.; Kolasinski, W. A.; "A method for characterizing a microprocessor's vulnerability to SEU", IEEE Transactions on Nuclear Science, Dec 1988 v 35 n 6.
- SEU Characterization of Digital Circuits Using Weighted Test Programs
- Analysis of Application Behavior During Fault Injection
- Flight Linux Project
- SEU related masters theses and doctoral dissertations
- R. Islam (2011). High-speed Energy-efficient Soft Error Tolerant Flip-flops (masters). Concordia University (M. A. Sc. Thesis).
- T. Z. Fullem (2006). Radiation detection using single event upsets in memory chips. Binghamton University (M. S. Thesis). ISBN 978-0-542-78484-2. ProQuest 304928976.
- C. L. Howe (2005). Radiation-induced energy deposition and single event upset error rates in scaled microelectronic structures. Vanderbilt University (M. S. Thesis).
- J. A. Thompson (1997). Design, Construction and Programming of a Microcontroller-Based Testbench Suitable for Radiation Testing of Microelectronic Circuits. Naval Postgraduate School (M. S. Thesis).
- D. R. Roth (1991). The role of charge collection in the single event upset. Clemson University (M. S. Thesis).
- A. G. Costantine (1990). An Advanced Single Event Upset Tester. Rensselaer Polytechnic Institute (Ph. D Thesis).