|Transistors||10 nm transistors|
|Instructions||MMX, AES-NI, CLMUL, FMA3|
Cannonlake (formerly Skymont) is Intel's codename for the 10 nanometer die shrink of Intel's Skylake microarchitecture, expected to be released in 2017. It is expected Intel will release one more 14 nm generation called Kaby Lake before the 10 nm shrink. As a die shrink, Cannonlake is a "tick" in Intel's tick-tock execution plan as the next step in semiconductor fabrication.
Cannonlake will be used in conjunction with Intel 200 Series chipsets, also known as Union Point. The platform as a whole will be named Union Bay.
Following Intel's longstanding Tick-Tock strategy, the replacement for Cannonlake would be a new architecture at the same 10 nm process node, delivered a year after Cannonlake. As of June 2015[update], confirmation of this has not been leaked or announced.
It has been speculated for a long time that reaching smaller process nodes would become impractical, leading to the end of Moore's Law. Intel however believes that it will be possible to reach at least 7 nm, though it will perhaps require use of materials other than silicon, such as indium gallium arsenide (InGaAs).
- "Intel's 10nm 'Cannonlake' delayed, replaced by 14nm 'Kaby Lake'". techspot. Retrieved 25 June 2015.
- "Intel's Cannonlake 10nm Microarchitecture is Due For 2016 - Compatible On Union Bay With Union Point PCH". WCCFTech. Retrieved 24 September 2014.
- "Intel forges ahead to 10nm, will move away from silicon at 7nm". Ars Technica.