|Created||Second half of 2017|
|Transistors||10 nm transistors|
|Instructions||MMX, AES-NI, CLMUL, FMA3|
Cannonlake (formerly Skymont) is Intel's codename for the 10-nanometer die shrink of Skylake, expected to be released in the 2nd half of 2017. As a die shrink, Cannonlake is a "tick" in Intel's "tick-tock" execution plan as the next step in semiconductor fabrication. Cannonlake will be used in conjunction with Intel 200 Series chipsets, also known as Union Point. The platform as a whole will be named Union Bay.
Following Intel's longstanding "tick-tock" strategy, the replacement for Cannonlake would be a new architecture at the same 10 nm process node, delivered a year after Cannonlake. As of August 2015[update], confirmation of this has not been leaked or announced.
It has been speculated for a long time that reaching smaller process nodes would become impractical, leading to the end of Moore's Law. Intel however believes that it will be possible to reach at least 7 nm, though it will perhaps require use of materials other than silicon, such as indium gallium arsenide (InGaAs).
- "Intel confirms tick-tock-shattering Kaby Lake processor as Moore’s Law falters". Ars Technica. 2015-07-16.
- "Intel to launch 10nm chips in early 2017". Gulfnews.com. January 20, 2015.
'The 10nm chips are expected to be launched early 2017,' said Taha Khalifa, general manager for Intel in the Middle East and North Africa region.
- "Intel's Cannonlake 10nm Microarchitecture is Due For 2016 - Compatible On Union Bay With Union Point PCH". WCCFTech. 2014-06-06. Retrieved 24 September 2014.
- "Intel forges ahead to 10nm, will move away from silicon at 7nm". Ars Technica. 2015-02-23.