Smart Response Technology
This article needs to be updated.(January 2014)
In computing, Smart Response Technology (SRT, also called SSD Caching before it was launched) is a proprietary caching mechanism introduced in 2011 by Intel for their Z68 chipset (for the Sandy Bridge–series processors), which allows a SATA solid-state drive (SSD) to function as cache for a (conventional, magnetic) hard disk drive (HDD).
SRT is managed by Intel Rapid Storage Technology software version 10.5 or later, and implemented both in its device driver and in the Z68 motherboard's firmware (option ROM). It is available only when the (integrated) disk controller is configured in RAID mode (but not AHCI or IDE modes) by implementing a style of RAID 0 striping. The user can select write-back (so-called maximized mode) or write-through (so-called enhanced mode) caching strategy. The maximum utilizable cache size on the SSD is 64 GB. Caching is done at the logical block addressing (LBA) level, not the file level.
Shortly before the announcement of the new chipset, Intel also introduced the Intel 311 (Larson Creek), a 20 GB single-level cell (SLC) solid-state drive, which it markets as suitable for caching. As of 2014[update], TRIM garbage collection is not supported for SRT caching devices, so the SSD's performance is solely maintained by its own firmware.
With the release of Ivy Bridge chipsets, support for SRT was provided in a larger variety of desktop chipsets, including Z77, Q77 and H77 (but not Z75, Q75 or B75) as long as an "Intel Core Processor" is used. The situation is similar for Haswell desktop chipsets, with Z87, Q87 and H87 listed as supported. The Ivy Bridge-E chipset X79 did not officially support SRT at launch, but some companies like ASRock added support to their boards via BIOS updates. The arrival of Ivy Bridge also saw SRT support added to mobile chipsets: QS77, QM77, UM77 and HM77 support SRT, while HM76 does not.
As of 2012[update], SRT was limited to using at most 64 GB for caching, meaning that on larger SSDs the rest remains unused by the cache. The chipset exposes any excess storage space as a separate independent disk, which can be used for other purposes.
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