Socket FM2+

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Socket FM2+
Chip form factors PGA
Contacts 906
Predecessor FM2
Successor AM4

This article is part of the CPU socket series

Socket FM2+ (FM2b) is a CPU socket used by AMD's desktop "Kaveri" APUs (Steamroller-based) and Godavari APUs (Steamroller-based) to connect to the motherboard. The FM2+ has a slightly different pin configuration to Socket FM2 with two additional pin sockets. Socket FM2+ APUs are not compatible with Socket FM2 motherboards due to the aforementioned additional pins. However, socket FM2 APUs such as "Richland" and "Trinity" are compatible with FM2+ socket.[1]

  • ECC DIMMs are supported on Socket FP3 but not supported on the Socket FM2+ package. GDDR5 or HBM memory are not supported.[2]
  • There are 3 PCI Express cores: one 2 ×16 core and two 5 ×8 cores, for a total of 64 lanes. There are 8 configurable ports, which can be divided into 2 groups:
    • Gfx-group: contains 2 ×8 ports. Each port can be limited to lower link widths for applications that require fewer lanes. Additionally, the two ports can be combined to create a single ×16 link.
    • GPP-group: contains 1 ×4 UMI and 5 General Purpose Ports (GPP).

All PCIe links are capable of supporting PCIe 2.x data rates. In addition, the Gfx link is capable of supporting PCIe 3.x data rate.[2]

For available chipsets consult Fusion controller hubs (FCH).

Its mobile counterpart is Socket FP3 (BGA-???).

Feature overview[edit]

Features of AMD Accelerated Processing Units
Brand Llano Trinity Richland Kaveri Carrizo Bristol Ridge Raven Ridge Desna, Ontario, Zacate Kabini, Temash Beema, Mullins Carrizo-L Stoney Ridge
Platform Desktop, Mobile Mobile Desktop, Mobile Ultra-mobile
Released Aug 2011 Oct 2012 Jun 2013 Jan 2014 Jun 2015 Jun 2016 TBA Jan 2011 May 2013 Q2 2014 May 2015 June 2016
Fab. (nm) GlobalFoundries 32 SOI 28 14 TSMC 40 28
Die size (mm2) 228 246 245 244.62 250.04 TBA 75 (+ 28 FCH) ~107 TBA 125
Socket FM1, FS1 FM2, FS1+, FP2 FM2+, FP3 FM2+, FP4 AM4, FP4 AM4, FP5 FT1 AM1, FT3 FT3b FP4 FP4
CPU architecture AMD 10h Piledriver Steamroller Excavator Zen Bobcat Jaguar Puma Puma+[3] Excavator
Memory support DDR3-1866
Up to
3D engine[a] TeraScale (VLIW5) TeraScale (VLIW4) GCN 2nd Gen (Mantle, HSA) GCN 3rd Gen (Mantle, HSA) GCN 5th Gen[4] (Mantle, HSA) TeraScale (VLIW5) GCN 2nd Gen GCN 3rd Gen[4]
Up to 400:20:8 Up to 384:24:6 Up to 512:32:8 TBA 80:8:4 128:8:4 Up to 192:?:?
Unified Video Decoder UVD 3 UVD 4.2 UVD 6 TBA UVD 3 UVD 4 UVD 4.2 UVD 6 UVD 6.3
Video Coding Engine N/A VCE 1.0 VCE 2.0 VCE 3.1 TBA N/A VCE 2.0 VCE 3.1
GPU power saving PowerPlay PowerTune N/A PowerTune[6]
Max. displays[b] 2–3 2–4 2–4 3 4 TBA 2 TBA TBA
TrueAudio N/A Yes[8] N/A[5] TBA
FreeSync N/A Yes N/A TBA
/drm/radeon[9][10] Yes N/A Yes N/A
/drm/amdgpu[11] N/A Yes[12] Yes N/A Yes[12] Yes
  1. ^ Unified shaders : texture mapping units : render output units
  2. ^ To feed more than two displays, the additional panels must have native DisplayPort support.[7] Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.

External links[edit]

  1. ^ Niels Broekhuijsen. "Report: Upcoming Socket FM2+ Will Support Older Trinity and Richland APUs". Tom's Hardware. 
  2. ^ a b "49125_15h_Models_30h-3Fh_BKDG" (pdf). AMD. 
  3. ^ "AMD Mobile “Carrizo” Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015" (Press release). 2014-11-20. Retrieved 2015-02-16. 
  4. ^ a b "AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". Retrieved 6 June 2017. 
  5. ^ a b Thomas De Maesschalck (2013-11-14). "AMD teases Mullins and Beema tablet/convertibles APU". Retrieved 2015-02-24. 
  6. ^ Tony Chen; Jason Greaves, "AMD's Graphics Core Next (GCN) Architecture" (PDF), AMD, retrieved 2016-08-13 
  7. ^ "How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card?". AMD. Retrieved 2014-12-08. 
  8. ^ "A technical look at AMD’s Kaveri architecture". Semi Accurate. Retrieved 6 July 2014. 
  9. ^ Airlie, David (2009-11-26). "DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33". Retrieved 2016-01-16. 
  10. ^ "Radeon feature matrix". Retrieved 2016-01-10. 
  11. ^ Deucher, Alexander (2015-09-16). "XDC2015: AMDGPU" (PDF). Retrieved 2016-01-16. 
  12. ^ a b Michel Dänzer (2016-11-17). "[ANNOUNCE] xf86-video-amdgpu 1.2.0".