The southbridge is one of the two chips in the core logic chipset on a personal computer (PC) motherboard, the other being the northbridge. The southbridge typically implements the slower capabilities of the motherboard in a northbridge/southbridge chipset computer architecture. In systems with Intel chipsets, the southbridge is named I/O Controller Hub (ICH), while AMD has named its southbridge Fusion Controller Hub (FCH) since the introduction of its Fusion AMD Accelerated Processing Unit (APU) while moving the functions of the Northbridge onto the CPU die, hence making it similar in function to the Platform hub controller.
The southbridge can usually be distinguished from the northbridge by not being directly connected to the CPU. Rather, the northbridge ties the southbridge to the CPU. Through the use of controller integrated channel circuitry, the northbridge can directly link signals from the I/O units to the CPU for data control and access.
Due to the push for system-on-chip (SoC) processors, modern devices increasingly have the northbridge integrated into the CPU die itself;[further explanation needed] examples are Intel's Sandy Bridge and AMD's Fusion processors, both released in 2011. The southbridge became redundant and it was replaced by the Platform Controller Hub (PCH) architecture introduced with the Intel 5 Series chipset in 2008 while AMD did the same with the release of their first APUs in 2011, naming the PCH the Fusion controller hub (FCH), which was only used on AMD's APUs until 2017 when it began to be used on AMD's Zen architecture while dropping the FCH name. On Intel platforms, all southbridge features and remaining I/O functions are managed by the PCH which is directly connected to the CPU via the Direct Media Interface (DMI). Intel low power processor (Haswell-U and onward) and Ultra low power processor (Haswell-Y and onward) also integrated an on-package PCH. Based on its Chiplet design, AMD Ryzen processor also integrated some southbridge function, such as some USB interface and some SATA/NVMe interface.
A southbridge chipset handled many of a computer's I/O functions, such as USB, Audio, the system BIOS, the ISA bus or the LPC bus, the low speed PCI/PCIe bus, the IOAPIC interrupt controller, the SATA storage, the historical PATA storage, and the NVMe storage. Different combinations of Southbridge and Northbridge chips are possible, but these two kinds of chips must be designed to work together; there is no industry-wide standard for interoperability between different core logic chipset designs. In 1990s and early 2000s, the interface between a northbridge and southbridge was the PCI bus. The main bridging interfaces used now are DMI (Intel) and UMI (AMD).
The name is derived from representing the architecture in the fashion of a map and was first described as such with the introduction of the PCI Local Bus Architecture in 1991. At Intel, the authors of the PCI specification viewed the PCI local bus as being at the very centre of the PC platform architecture (i.e., at the Equator).
The northbridge extends to the north of the PCI bus backbone in support of CPU, memory/cache, and other performance-critical capabilities. Likewise the southbridge extends to the south of the PCI bus backbone and bridges to less performance-critical I/O capabilities such as the disk interface, audio, etc.
The CPU is located at the top of the map at due north. The CPU is connected to the chipset via a fast bridge (the northbridge) located north of other system devices as drawn. The northbridge is connected to the rest of the chipset via a slow bridge (the southbridge) located south of other system devices as drawn.
Although the current PC platform architecture has replaced the PCI bus backbone with faster I/O backbones, the bridge naming convention remains.
- PCI bus. A south bridge may also include support for PCI-X.
- Low speed PCI Express (PCIe) interfaces usually for Ethernet and NVMe.
- ISA bus or LPC bridge. ISA slots are no longer provided on more recent motherboards. The LPC bridge provides a data and control path to the super I/O (the normal attachment for the PS/2 keyboard and mouse, parallel port, serial port, IR port, and floppy controller).
- SPI bus. The SPI bus is a simple serial bus mostly used for firmware (e.g., BIOS/UEFI) flash storage access.
- SMBus controller.
- DMA controller. The 8237 DMA controller allows ISA or LPC devices direct access to main memory without needing help from the CPU.
- PIC and I/O APIC.
- Mass storage interfaces such as SATA, M.2, and historical PATA. This typically allows attachment of hard drives or SSDs.
- Real-time clock.
- Programmable interval timer.
- High Precision Event Timer.
- ACPI controller or APM controller.
- Nonvolatile BIOS memory. The system CMOS (BIOS configuration memory), assisted by battery supplemental power, creates a limited non-volatile storage area for BIOS configuration data.
- Intel HD Audio or AC'97 sound interface.
- USB interfaces.
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