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Stepping level refers to the introduction or revision of the photolithographic photomask or masks within the set of plates that generate the pattern that produces an integrated circuit. The term originated from the name of the equipment ("steppers") that exposes the photoresist to light. Integrated circuits have two primary classes of mask sets: 1. base layers that are used to build the structures that make up the logic such as transistors, and 2: metal layers that connect the logic together.
Typically, when an integrated circuit manufacturer such as Intel or AMD invests money to do a stepping (i.e. a revision to the masks), they have found bugs in the logic, have made improvements to the design that allow for faster processing, have found a way to increase yield or improve the "bin splits" (i.e., create faster transistors and hence faster CPUs), improve maneuverability to more easily identify marginal circuits, or reduce test time which can reduce the cost of testing the part.
Many integrated circuits have a means of interrogating them in order to discover their stepping level. For example, on x86 CPUs executing the CPUID with the EAX register set to '1' will place values in other registers that show the CPU's stepping level.
Stepping identifiers are commonly an alphabetic letter followed by a numeric number, for example "B2." Usually, the letter indicates the revision level of a chip's base layers and the number indicates the revision level of the metal layers. A change in the letter indicates a change to the base layer mask revision and metal layers, while a change in the number indicates a metal-layer–only mask revision. An analogy is the major/minor revision numbers used in software versioning. Base layer revision changes are time consuming and more expensive for the manufacturer, but some fixes are difficult or impossible to accomplish with metal-only changes to the integrated circuit.
The Intel Core microarchitecture uses a number of steppings, which unlike previous microarchitectures not only represent incremental improvements but also different sets of features like cache size and low power modes. Most of these steppings are used across brands, typically by disabling some of the features and limiting clock frequencies on low-end chips. Steppings with a reduced cache size use a separate naming scheme, which means that the releases are no longer in alphabetic order.
- "From Sand to Silicon "Making of a Chip" Illustrations" (PDF). Intel. May 2009. Retrieved July 25, 2014.
- Seth P. Bates (2000). "Silicon Wafer Processing" (PDF). gatech.edu. Archived from the original (PDF) on 2015-06-16. Retrieved July 25, 2014.
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