Steve Furber

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Steve Furber
Steve Furber.jpg
Steve Furber
Born Stephen Byram Furber
(1953-03-21) 21 March 1953 (age 61)[1]
Manchester[2]
Nationality British
Fields
Institutions
Alma mater St John's College, Cambridge[1]
Thesis Is the Weis-Fogh principle exploitable in turbomachines? (1979)
Doctoral advisor John Ffowcs Williams[4]
Doctoral students
Other notable students Simon Segars
(CEO of ARM)[54]
Known for
Notable awards
Website
apt.cs.man.ac.uk/people/sfurber
www.manchester.ac.uk/research/steve.furber

Stephen Byram "Steve" Furber CBE, FRS, FREng (born 1953) is the ICL Professor of Computer Engineering at the School of Computer Science at the University of Manchester[61] and is probably best known for his work at Acorn Computers, where he was one of the designers of the BBC Micro and the ARM 32-bit RISC microprocessor.[3][62][63][57][64][65][66]

Education[edit]

Furber was educated at Manchester Grammar School and represented the UK in the International Mathematical Olympiad in Hungary in 1970 and won a bronze medal.[67] He went on to study the Cambridge Mathematical Tripos at St John's College, Cambridge, receiving a Bachelor of Arts degree in mathematics in 1974. In 1978, he was appointed the Rolls-Royce Research Fellow in Aerodynamics at Emmanuel College, Cambridge and was awarded a PhD in 1980 on the fluid dynamics of the Weis-Fogh principle.[68][69]

Acorn Computers, BBC Micro and ARM[edit]

From 1980 to 1990, Furber worked at Acorn Computers where he was a Hardware Designer and then Design Manager. He was a principal designer of the BBC Micro and the ARM microprocessor. In August 1990 he moved to the University of Manchester to become the ICL Professor of Computer Engineering and established the Amulet research group.

Research[edit]

In 2003, Furber was a member of the EPSRC research cluster in biologically-inspired[70] novel computation. On 16 September 2004, he gave a speech on Hardware Implementations of Large-scale Neural Networks as part of the initiation activities of the Alan Turing Institute.

Furber's latest project is known as SpiNNaker (Spiking Neural Network Architecture),[55][71][72] also nicknamed the "brain box", to be constructed at the University of Manchester. This is an attempt to build a new kind of computer that directly mimics the workings of the human brain. Spinnaker is essentially an artificial neural network realised in hardware, a massively parallel processing system eventually designed to incorporate a million ARM processors.[73][74] The finished Spinnaker will model 1 per cent of the human brain's capability, or around 1 billion neurons. The Spinnaker project[75] aims amongst other things to investigate:

  • How can massively parallel computing resources accelerate our understanding of brain function?
  • How can our growing understanding of brain function point the way to more efficient parallel, fault-tolerant computation?

Furber believes that "significant progress in either direction will represent a major scientific breakthrough".[75]

Furber's research interests include asynchronous systems, ultra-low-power processors for sensor networks, on-chip interconnect and globally asynchronous locally synchronous (GALS),[76] and neural systems engineering.[77]

Awards and honours[edit]

A significant part of Furber's research is funded by grants that have been awarded by the EPSRC.[78] In February 1997, Furber was elected a Fellow of the British Computer Society. In 1998, he became a member of the European Working Group on Asynchronous Circuit Design (ACiD-WG). In 2002, he was elected a Fellow of the Royal Society and was Specialist Adviser to the House of Lords Science and Technology Select Committee inquiry into microprocessor technology.

Furber is a Fellow of the Royal Academy of Engineering, the IEEE (2005) and the IET, and is a Chartered Engineer. In September 2007 he was awarded the prestigious IET Faraday Medal. In 2010 he gave the IET Pinkerton Lecture.

Furber was appointed Commander of the Order of the British Empire (CBE) in the 2008 New Year Honours[79][80] and was elected as one of the three laureates of Millennium Technology Prize in 2010 (with Richard Friend and Michael Grätzel), for development of ARM processor.[81]

In 2012, Furber was made a Fellow of the Computer History Museum "for his work, with Sophie Wilson, on the BBC Micro computer and the ARM processor architecture."[82][83]

In 2014, he was made a Distinguished Fellow at the British Computer Society (DFBCS) recognising his contribution to the IT profession and industry, joining the likes of Bill Gates, Tim Berners Lee, Vint Cerf and Tom Kilburn.[60]

Furber's nomination for the Royal Society reads:

Professor Furber is distinguished for his fundamental contributions to the design and analysis of electronic systems, especially microprocessors. He was the original designer of the hardware architecture of the ARM processor, the world's leading embedded processor core and a major engineering and commercial success for the United Kingdom. Having moved to Manchester University, he established a research team to investigate asynchronous processor design, which rapidly made fundamental contributions to the field. He has shown how to combine academic design theories with practical engineering constraints to achieve a remarkable and elegant synthesis. His work demonstrates in particular how to design microprocessors with low power and low radio frequency emissions, necessary for future wireless applications. Furber has designed a series of highly original asynchronous processors to execute the ARM instruction set. These have been fabricated and subjected to extensive experimental analysis. Furber's group is the world's leading centre of research in both fundamental theory and engineering implementation of such devices.[58]

Furber was played by actor Sam Philips in the BBC Four documentary drama Micro Men,[84] first aired on 8 October 2009.

References[edit]

  1. ^ a b "FURBER, Prof. Stephen Byram" (Who's Who 2013, A & C Black, an imprint of Bloomsbury Publishing plc, 2013; online edn, Oxford University Press).  (subscription required)
  2. ^ Brown, David (February 1, 2010). "A Conversation with Steve Furber". Queue. Association for Computing Machinery. Retrieved March 7, 2012. 
  3. ^ a b List of publications from Google Scholar
  4. ^ Steve Furber at the Mathematics Genealogy Project
  5. ^ Bainbridge, W. J.; Furber, S. B. (2001). "Delay insensitive system-on-chip interconnect using 1-of-4 data encoding". Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001. p. 118. doi:10.1109/ASYNC.2001.914075. ISBN 0-7695-1034-5. 
  6. ^ Bainbridge, J.; Furber, S. (2002). "Chain: A delay-insensitive chip area interconnect". IEEE Micro 22 (5): 16. doi:10.1109/MM.2002.1044296. 
  7. ^ Bainbridge, William John (2000). Asynchronous system-on-chip interconnect (PhD thesis). University of Manchester (CPHC/BCS distinguished dissertation winner). ISBN 9781852335984. 
  8. ^ Bose, J.; Furber, S. B.; Shapiro, J. L. (2005). "An associative memory for the on-line recognition and prediction of temporal sequences". Proceedings. 2005 IEEE International Joint Conference on Neural Networks, 2005 2. p. 1223. doi:10.1109/IJCNN.2005.1556028. ISBN 0-7803-9048-2. 
  9. ^ Bose, Joy (2007). Engineering a sequence machine through spiking neurons employing rank-order codes (PhD thesis). University of Manchester. 
  10. ^ Davies, S.; Galluppi, F.; Rast, A. D.; Furber, S. B. (2012). "A forecast-based STDP rule suitable for neuromorphic implementation". Neural Networks 32: 3–14. doi:10.1016/j.neunet.2012.02.018. PMID 22386500. 
  11. ^ Davies, Sergio (2013). Learning in Spiking Neural Networks (PhD thesis). University of Manchester. 
  12. ^ Emmons, Christopher Daniel (2010). Exploiting concurrency in a general purpose one-instruction computer architecture (PhD thesis). University of Manchester. 
  13. ^ Endecott, Philip Brian (1996). SCALP: a superscalar asynchronous low-power processor (PhD thesis). University of Manchester. 
  14. ^ Felicijan, T.; Furber, S. B. (2004). "An asynchronous on-chip network router with quality-of-service (QoS) support". IEEE International SOC Conference, 2004. Proceedings. p. 274. doi:10.1109/SOCC.2004.1362432. ISBN 0-7803-8445-8. 
  15. ^ Felicijan, Tomaz (2004). Quality-of-Service (QoS) for asynchronous On-Chip Networks (PhD thesis). University of Manchester. 
  16. ^ Galluppi, Francesco (2013). Information Representation on a Universal Neural Chip (PhD thesis). University of Manchester. 
  17. ^ Galluppi, F.; Davies, S.; Rast, A.; Sharp, T.; Plana, L. A.; Furber, S. (2012). "A hierachical configuration system for a massively parallel neural hardware platform". Proceedings of the 9th conference on Computing Frontiers - CF '12. p. 183. doi:10.1145/2212908.2212934. ISBN 9781450312158. 
  18. ^ Rast, A.; Galluppi, F.; Davies, S.; Plana, L.; Patterson, C.; Sharp, T.; Lester, D.; Furber, S. (2011). "Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware". Neural Networks 24 (9): 961–978. doi:10.1016/j.neunet.2011.06.014. PMID 21778034. 
  19. ^ Grymel, Martin Thomas (2013). Error Control With Binary Cyclic Codes (PhD thesis). University of Manchester. 
  20. ^ Grymel, M.; Furber, S. B. (2011). "A Novel Programmable Parallel CRC Circuit". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (10): 1898. doi:10.1109/TVLSI.2010.2058872. 
  21. ^ Hormdee, D.; Garside, J. D.; Furber, S. B. (2003). "An asynchronous copy-back cache architecture". Microprocessors and Microsystems 27 (10): 485. doi:10.1016/S0141-9331(03)00101-7. 
  22. ^ Hormdee, Daranee (2002). Copy-back cache organisation for an asynchronous microprocessor (PhD thesis). University of Manchester. 
  23. ^ Xin Jin; Lujan, M.; Plana, L. A.; Davies, S.; Temple, S.; Furber, S. B. (2010). "Modeling Spiking Neural Networks on SpiNNaker". Computing in Science & Engineering 12 (5): 91. doi:10.1109/MCSE.2010.112. 
  24. ^ Jin, Xin (2010). Parallel simulation of neural networks on SpiNNaker universal neuromorphic hardware (PhD thesis). University of Manchester. 
  25. ^ Khan, M. M.; Lester, D. R.; Plana, L. A.; Rast, A.; Jin, X.; Painkras, E.; Furber, S. B. (2008). "SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor". 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence). p. 2849. doi:10.1109/IJCNN.2008.4634199. ISBN 978-1-4244-1820-6. 
  26. ^ Khan, Muhammad Mukaram (2009). Configuring a massively parallel CMP system for real-time neural applications (PhD thesis). University of Manchester. 
  27. ^ Liu, Jianwei (1997). Arithmetic and control components for an asynchronous system (PhD thesis). University of Manchester. 
  28. ^ Yijun Liu; Furber, S. (2005). "A Low Power Embedded Dataflow Coprocessor". IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05). p. 246. doi:10.1109/ISVLSI.2005.9. ISBN 0-7695-2365-X. 
  29. ^ Liu, Yijun (2005). Power-efficient embedded processing (PhD thesis). University of Manchester. 
  30. ^ Okoyo, Henry Okora (1998). A synaptic logic neuron model (PhD thesis). University of Manchester. 
  31. ^ Painkras, Eustace (2013). A chip multiprocessor for a large-scale neural simulator (PhD thesis). University of Manchester. 
  32. ^ Patterson, C.; Garside, J.; Painkras, E.; Temple, S.; Plana, L. A.; Navaridas, J.; Sharp, T.; Furber, S. (2012). "Scalable communications for a million-core neural processing architecture". Journal of Parallel and Distributed Computing 72 (11): 1507. doi:10.1016/j.jpdc.2012.01.016. 
  33. ^ Painkras, E.; Plana, L. A.; Garside, J.; Temple, S.; Davidson, S.; Pepper, J.; Clark, D.; Patterson, C.; Furber, S. (2012). "SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation". Proceedings of the IEEE 2012 Custom Integrated Circuits Conference. p. 1. doi:10.1109/CICC.2012.6330636. ISBN 978-1-4673-1556-2. 
  34. ^ Woods, J. V.; Day, P.; Furber, S. B.; Garside, J. D.; Paver, N. C.; Temple, S. (1997). "AMULET1: An asynchronous ARM microprocessor". IEEE Transactions on Computers 46 (4): 385. doi:10.1109/12.588033. 
  35. ^ Paver, Nigel Charles (1994). The design and implementation of an asynchronous microprocessor (PhD thesis). University of Manchester. 
  36. ^ Petlin, O. A.; Furber, S. B. (1995). "Scan testing of asynchronous sequential circuits". Proceedings. Fifth Great Lakes Symposium on VLSI. p. 224. doi:10.1109/GLSV.1995.516057. ISBN 0-8186-7035-5. 
  37. ^ Petlin, Oleg Alexandrovich (1996). Design for testability of asynchronous VLSI circuits (PhD thesis). University of Manchester. 
  38. ^ Patterson, C.; Preston, T.; Galluppi, F.; Furber, S. (2012). "Managing a Massively-Parallel Resource-Constrained Computing Architecture". 2012 15th Euromicro Conference on Digital System Design. p. 723. doi:10.1109/DSD.2012.84. ISBN 978-0-7695-4798-5. 
  39. ^ Patterson, James Cameron (2012). Managing a real-time massively-parallel neural architecture (PhD thesis). University of Manchester. 
  40. ^ Rast, A. D.; Shufan Yang; Khan, M.; Furber, S. B. (2008). "Virtual synaptic interconnect using an asynchronous network-on-chip". 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence). p. 2727. doi:10.1109/IJCNN.2008.4634181. ISBN 978-1-4244-1820-6. 
  41. ^ Rast, Alexander (2011). Scalable event-driven modelling architectures for neuromimetic hardware (PhD thesis). University of Manchester. 
  42. ^ Bhattacharya, B. S.; Furber, S. B. (2010). "Biologically Inspired Means for Rank-Order Encoding Images: A Quantitative Analysis". IEEE Transactions on Neural Networks 21 (7): 1087–1099. doi:10.1109/TNN.2010.2048339. PMID 20550988. 
  43. ^ Sen, B.; Furber, S. (2009). "Evaluating rank-order code performance using a biologically-derived retinal model". 2009 International Joint Conference on Neural Networks. p. 2867. doi:10.1109/IJCNN.2009.5178842. ISBN 978-1-4244-3548-7. 
  44. ^ Sen, Basabdatta (2008). Information recovery from rank-order encoded images (PhD thesis). University of Manchester. 
  45. ^ Sharp, Tom (2013). Real-Time Million-Synapse Simulation of Cortical Tissue (PhD thesis). University of Manchester. 
  46. ^ Sharp, T.; Patterson, C.; Furber, S. (2011). "Distributed configuration of massively-parallel simulation on SpiNNaker neuromorphic hardware". The 2011 International Joint Conference on Neural Networks. p. 1099. doi:10.1109/IJCNN.2011.6033346. ISBN 978-1-4244-9635-8. 
  47. ^ Sharp, T.; Galluppi, F.; Rast, A.; Furber, S. (2012). "Power-efficient simulation of detailed cortical microcircuits on SpiNNaker". Journal of Neuroscience Methods 210 (1): 110–118. doi:10.1016/j.jneumeth.2012.03.001. PMID 22465805. 
  48. ^ Shi, Y.; Furber, S. B.; Garside, J.; Plana, L. A. (2009). "Fault Tolerant Delay Insensitive Inter-chip Communication". 2009 15th IEEE Symposium on Asynchronous Circuits and Systems. p. 77. doi:10.1109/ASYNC.2009.21. ISBN 978-0-7695-3616-3. 
  49. ^ Shi, Yebin (2010). Fault-tolerant delay-insensitive communication (PhD thesis). University of Manchester. 
  50. ^ Wu, J.; Furber, S. (2009). "A Multicast Routing Scheme for a Universal Spiking Neural Network Architecture". The Computer Journal 53 (3): 280. doi:10.1093/comjnl/bxp024. 
  51. ^ Wu, Jian (2010). Router for massively-parallel neural simulation (PhD thesis). University of Manchester. 
  52. ^ Yang, Shufan (2010). Memory interconnect management on a chip multiprocessor (PhD thesis). University of Manchester. 
  53. ^ Yu, Zongchuan (2004). Investigation into the security of self-timed circuits (PhD thesis). University of Manchester. 
  54. ^ Segars, Simon Anthony (1996). Low power microprocessor design (MSc thesis). University of Manchester. 
  55. ^ a b Furber, S. B.; Galluppi, F.; Temple, S.; Plana, L. A. (2014). "The SpiNNaker Project". Proceedings of the IEEE: 1. doi:10.1109/JPROC.2014.2304638. 
  56. ^ "The Human Brain Project SP 9: Neuromorphic Computing Platform" on YouTube
  57. ^ a b Furber, Stephen B. (2000). ARM system-on-chip architecture. Boston: Addison-Wesley. ISBN 0-201-67519-6. 
  58. ^ a b "Library and Archive Catalogue EC/2002/10: Furber, Stephen Byram". London: The Royal Society. Archived from the original on 2014-03-17. 
  59. ^ BCS Lovelace Medal
  60. ^ a b Sarah Chatwin (2014-03-14). "Professor Steve Furber – BCS Distinguished Fellow". [Computer Science Manchester]. Retrieved 2014-03-14. 
  61. ^ "Prof Stephen Furber (CBE FRS FREng FBCS FIET CITP CEng), research profile – personal details (The University of Manchester)". Retrieved 2012-06-11. 
  62. ^ List of publications from Microsoft Academic Search
  63. ^ List of publications from the DBLP Bibliography Server
  64. ^ Furber, Stephen B. (1989). VLSI RISC architecture and organization. New York: M. Dekker. ISBN 0-8247-8151-1. 
  65. ^ Steve Furber on Twitter
  66. ^ Steve Furber from the Scopus bibliographic database
  67. ^ Steve Furber's results at the International Mathematical Olympiad
  68. ^ Furber, S. B.; Williams, J. E. F. (1979). "Is the Weis-Fogh principle exploitable in turbomachinery?". Journal of Fluid Mechanics 94 (3): 519. doi:10.1017/S0022112079001166. 
  69. ^ Fitzpatrick, J. (2011). "An interview with Steve Furber". Communications of the ACM 54 (5): 34. doi:10.1145/1941487.1941501. 
  70. ^ Furber, S. (2006). "Living with Failure: Lessons from Nature?". Eleventh IEEE European Test Symposium (ETS'06). pp. 4–0. doi:10.1109/ETS.2006.28. ISBN 0-7695-2566-0. 
  71. ^ Xin Jin; Furber, S. B.; Woods, J. V. (2008). "Efficient modelling of spiking neural networks on a scalable chip multiprocessor". 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence). pp. 2812–2819. doi:10.1109/IJCNN.2008.4634194. ISBN 978-1-4244-1820-6. 
  72. ^ Dempsey, Paul (March 15, 2011). "SpiNNaker set to receive new 18-core SoC to help reverse engineer the human brain.". Engineering and Technology Magazine (Institution of Engineering and Technology). Retrieved March 7, 2012. 
  73. ^ Bush, Steve (2011-07-08). "One million ARM cores to simulate brain at Manchester". Electronics Weekly. Retrieved 2011-07-11. "UK scientists aim to model 1 per cent of a human brain with up to one million ARM cores. ... ARM was approached in May 2005 to participate in SpiNNaker ... agreement extends to Manchester making enough chips for a computer with a million cores." 
  74. ^ "Acorn's Steve Furber looks to ARM supercomputers: A million node supercomputer". Techgineering. techgineering.org. July 8, 2011. Retrieved March 7, 2012. 
  75. ^ a b Furber, S. (2011). Biologically-Inspired Massively-Parallel Architectures: A Reconfigurable Neural Modelling Platform 6578. pp. 2–2. doi:10.1007/978-3-642-19475-7_2. 
  76. ^ Plana, L. A.; Furber, S. B.; Temple, S.; Khan, M.; Shi, Y.; Wu, J.; Yang, S. (2007). "A GALS Infrastructure for a Massively Parallel Multiprocessor". IEEE Design & Test of Computers 24 (5): 454. doi:10.1109/MDT.2007.149.  edit
  77. ^ Temple, S.; Furber, S. (2007). "Neural systems engineering". Journal of the Royal Society Interface 4 (13): 193. doi:10.1098/rsif.2006.0177. 
  78. ^ http://gow.epsrc.ac.uk/NGBOViewPerson.aspx?PersonId=5628 Grants awarded to Steve Furber by the Engineering and Physical Sciences Research Council
  79. ^ BBC News: One of the designers of the classic BBC Micro computer has been recognised in the New Year Honours list
  80. ^ BBC Micro designer gets New Year's Honour ZDNet 2-Jan-2008
  81. ^ "Professor Stephen Furber: Creator of the ARM microprocessor". Millennium Prize. 9 June 2010. Retrieved 10 June 2010. 
  82. ^ "Steve Furber". Computer History Museum. Retrieved 2013-05-23. 
  83. ^ Williams, Alun (January 20, 2012). "Four ARM cores for every person on earth – Furber, Wilson honoured". Electronics Weekly. Retrieved March 7, 2012. 
  84. ^ Micro Men (TV 2009) at the Internet Movie Database

External links[edit]

Academic offices
Preceded by
Brian Warboys
Head of the School of Computer Science, University of Manchester
2001–2004
Succeeded by
Chris Taylor