|WikiProject Computing||(Rated Start-class, Low-importance)|
|This is the talk page for discussing improvements to the 4B5B article.|
This article should be listed in http://en.wikipedia.org/wiki/Category:Line_codes.
Done. --126.96.36.199 19:08, 7 December 2006 (UTC)
There's also a 5b6b code, used by some IEEE 802 class standard. A 5-bit input block makes a 6-bit , DC-balanced output block.
Output blocks are either DC-balanced (overall disparity 0), or are assigned in pairs, (overall disparity ±2). The latter codes are assigned in pairs, and the member of the pair chosen that will drive the running disparity toward 0.
Because input blocks have an odd number of bits, they always have an odd disparity. Blocks with a disparity of ±1 are output by appending one more bit, chosen to make the overall disparity 0.
Blocks with disparities ±3 and ±5 are assigned pairs of codes, as follows. Note that the pairs are bitwise complements, so the encoder only needs to store one value, and optionally invert it.
Why (0,3) RLL, when GCR gives (0,2) RLL?
One thing that's puzzled me is why FDDI chose a code with up to three zeros between ones (sync edges), when codes were already known (GCR) that limited. Does it have something to do with DC bias? But the code isn't DC-balanced... 188.8.131.52 (talk) 14:01, 13 March 2009 (UTC)
FDDI control codes
FDDI uses TT as Ending Delimiter for Tokens
FDDI uses TRRR as minimum End of Frame Sequence for Data Frames
Repeaters may change an R to an S
A received Data Frame is invalid if the first two symbols of the End of Frame Sequence are not TR
FDDI-II defines other control code sequences for Cycle Control and for Tokens and Data within the Packet Channel