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I made some argument about this. But I didn't do the job for my own because I'm not a native speaker of English. I want to see someone does that job. —Preceding unsigned comment added by Routitz (talkcontribs) 17:48, 5 April 2010 (UTC)

Would anyone object to putting overflow detection circuits for adder circuits in this article? The articles about overflow didn't seem quite the place to put information like this. Lordhatrus (talk) 16:32, 6 June 2008 (UTC)

## Carry-Skip and Carry-Select

The article carry-skip adder now exists, it used to be called carry-bypass adder (see the talk page for details). I've edited this article, and renamed the instance of carry-bypass adder to carry-skip (although still mentioning the alternative nomenclature). I didn't make any other changes, but want to point out that in the More complex adders section, there are duplicate links for the carry-skip and carry-select adders (they're mentioned in-line with the text, and on the line following which mentions "other adder designs". Bcastell (talk) 13:33, 10 December 2012 (UTC)

two questions: what is the difference between a carry-lookahead and a carry-propagate, which I have also heard of? Are they the same thing? Also, is the carrry select adder the same as the carry save adder? these can be confusing because they share the same acronym.

jUst wondering. Thanks for good work.

A carry-save adder is actually an architecture for adding more than 2 binary numbers together, like in a multiplier. I'm not certain, but I think a carry-propagate adder might be as well.

Ckape 03:03, 3 Jan 2005 (UTC)

## GG and PG

What's the GG and PG leaving the carry lookahead at the end of the carry lookahead block? Why do you not just have a single carry out from the lookahead block? Cheers.

## suggest changes

can i suggest some changes to the third paragraph:

i haven't changed the file myself as this is not really my area of expertise, but i think my changes make clearer the distinction between the full adder and the two half adders. otherwise there is some ambiguity. User:halio 13th dec 2005

i just looked further down the page and realised that the points i found confusing are better expressed by the diagrams than they are in the intro. perhaps this page needs a slight re-edit to create a more succinct intro, and to better integrate the more detailed explaination with the diagrams. User:halio 13th dec 2005

gah! why, on the image of the ripple carry adder, is the first line to the first 'B' crooked!?

I came to this page on a redirection from "Brent-Kung adder", but I see no reference to B&K. First of all, since the B&K cells are a way to implement a carry lookahead, the redirection should go there. Second, if it's not going to be discussed in the CLA adder page, then what's the point in a redirection?

BTW, a carry propagate adder is an adder where the carry is immediately added, as opposite to the carry save adder where two words (carry and sum) are kept separate till the end. All of the adders here described (ripple carry or lookahead) are carry propagate adders. And the carry select adder is a carry-propagate adder.

full adder has three inputs inp1,inp2 and carry.

The one u have stated is a half adder .

In my Logic Design book, it says a full adder has two inputs - not three like this article says. Is this article wrong on that? Fresheneesz 07:28, 13 March 2006 (UTC)

Yes, it's wrong. 76.99.125.152 (talk) 23:44, 22 November 2011 (UTC)

Is the picture for the full adder really ok? For C_out it implements C_out = (A and B) or (C_in and (A xor B)), which is not equivalent to the stated expression C_out = (A and B) or (C_in and (A or B)). The latter puts a 1 for C_in in the last row of the truth table, whereas the former puts a 0 there.

Note also that the note under the truth table does not concern this problem; A and B can both be 1 simultaneously.

—Preceding unsigned comment added by 129.16.80.10 (talk) 10:40, 18 January 2008 (UTC)

Yes, it's OK, but I think the expression for C_in should be changed to C_out = (A and B) or (C_in and (A or B)) = (A and B) or (C_in and (A xor B)) since the last part of this is what's really implemented.

The full adder picture has no arrows or lines in it at all when I look at it in the article. On the description page, I still see no lines. When I click the actual image URL I see the lines. What gives? Is it a browser error? (happens for me in Safari or Firefox 3 in MacOS X) Staecker (talk) 22:01, 10 December 2008 (UTC)

I see the lines fine -- must be something client-side. I agree that the full adder picture should be replaced, but on the grounds that it doesn't clearly show how it can be constructed of two half-adders and an OR gate. 152.78.170.144 (talk) 16:59, 23 January 2009 (UTC)

Is there any way this could be written in more layman terms? Thanks for the info! —Preceding unsigned comment added by 192.195.249.152 (talk) 03:50, 10 February 2010 (UTC)

-Basically it doesn't show that the full adder can be constructed out of half adders. —Preceding unsigned comment added by 91.109.163.67 (talk) 13:59, 13 March 2011 (UTC)

From the article revision History: [1]

The layout of ripple carry adder is simple, which allows for fast design time; however, the ripple carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder.
The gate delay can easily be calculated by inspection of the full adder circuit.
Each full adder requires three levels of logic. In a 32-bit [ripple carry] adder, there 32 full adders,so the critical path (worst case) delay is ${\displaystyle 32*3=96}$ gate delays.

I guess this part should be checked. The critical path doesn't occur in that path. Although that is the worst case in this situation, serially connected adders doesn't suffer from that path, because A OR B can be evaluated as soon as the signals come. The critical path occurs through the ${\displaystyle C_{o}}$ to ${\displaystyle C_{i}}$ root, which is the very signal that cannot be evaluated unless the previous stage is finished. The critical path delay of stage i is ${\displaystyle 2*i+1}$, where i > 0. And the first adder is stage 0 in this case.

My reference is "Contemporary Logic Design" which is written by Randy H. Katz.

written by User:Routitz moved to discussion by MichaelFrey (talk) 17:42, 7 April 2010 (UTC)

i have no idea what the official name is, but it is possible to make an effective adder by putting half adders into a pyramid. —Preceding unsigned comment added by 178.109.166.32 (talk) 18:07, 12 January 2011 (UTC)

## a mistake

The formula for carry [2] and the picture are not same. There is an OR between (x.y) and the other part not XOR. Marmzok (talk) 08:24, 24 June 2011 (UTC)

## Vandalism and Partial Reverts starting Sept 22nd turning into a mess

Ok, this is turning into a mess so I brought this to the attention of the talk page so I don't jump in and make things worse without first verifying I understand what's going on here. If I understand correctly:

1. At 5:59am we have a vandalizer.
2. At 6:10am we have the same vandalizer striking again.
3. At 7:25am we have a prompt reverter which undid the 6:10 edit but not to the 5:59 edit.
4. Then on Sept 23rd at 10:15pm someone noticed this then attempted to undo the 5:59 edit but only accomplished what appears to be a partial revert.

What do you feel would be the best coarse of action here? --Thelazyleo (talk) 09:09, 24 September 2012 (UTC)

If you see something wrong and you can fix it, Be Bold and fix it. Wikipedia didn't used to debate every comma and non-breaking space...--Wtshymanski (talk) 17:58, 24 September 2012 (UTC)

## The alternate form for the Carry Out seems to be the same form as the original Carry Out

The two methods for calculating Cout are the same. Both list the method as ${\displaystyle C_{out}=(A\cdot B)+(C_{in}\cdot (A\oplus B))}$ The text of the artical sates Using only two types of gates is convenient if the circuit is being implemented using simple IC chips which contain only one gate type per chip. In this light, Cout can be implemented as and it then lists the same methods above ${\displaystyle C_{out}=(A\cdot B)+(C_{in}\cdot (A\oplus B))}$. The second method contains 3 types of logic gates: AND, OR, and XOR.

Diff (This appears to be when it was changed) This change caused some sort of parser error and then the math code was changed again. Diff (point when the math code parsed correctly) This is the point where the two methods to calculate Cout became the same.

Maxximillian (talk) 21:57, 7 March 2013 (UTC)

As per the text the two methods shouldn't be the same as one is an alternate (simpler in terms of less type of logic gates) 96.244.142.3 (talk) 15:05, 8 March 2013 (UTC)

## critical path of a full adder: T_c = 2 D

isn't it T_c = 2 D + 1T_XOR = 5D? anyway, I am reading that for 1 single full (half) adder, internal (connection and logic gate) delays are dominated by I/O (package) delays; internal delays get propagated and therefore become relevant as several full adders are cascaded;

## Is "1-bit full adder" the correct term?

I saw it at transistor count (28 transistors for it) and looked here and saw in the picture. 28 transistor seems to be a degenerate case.. 1 bit+1 bit->2-bit right? [Wouldn't half adder do for one bit?] Should the that article (and the picture here) say "full adder (for every bit)"? Even if this is true this is the only example for adders and should be clarified and maybe half adders adden and more complex schemes that save compared to multi-bit full-adders (x28). And (ignoring the last bit and overflow etc) as that the transistor count you get - by multiplying by 28, the schematic picture for ripple-carry implies that if there is no overhead? Can you do even better with full adders? Anyone know best case for non-ripple for say 32 or 64 bit? comp.arch (talk) 09:59, 22 October 2014 (UTC)

Yes, "1 bit full adder" is the right term for a function that takes 3 input bits (often called A, B, and Cin) and outputs the sum as 2 output bits (the sum bit S and the carry bit Cout) as described in adder (electronics)#Full adder. That function cannot be implemented with only a single half adder.
Using "conventional" standard static CMOS with only pull-up and pull-down transistors, my understanding is that 28 transistors is the minimum number of transistors to implement a "1 bit full adder".[1][2][3]
(As those references point out, people have found a variety of ways to make such full adders using fewer transistors, such as using pass gates, also called transmission gates, and dynamic logic, etc. -- but each of these approaches has its own drawbacks).
Yes, you could implement a 16-bit ripple-carry adder out of such 28-transistor full adders using 16 full adders, using 16*28 = 448 transistors with no overhead.
1. ^ waset.org/publications/10516/a-novel-low-power-high-speed-14-transistor-cmos-full-adder-cell-with-50-improvement-in-threshold-loss-problem "A Novel Low Power, High Speed 14 Transistor CMOS Full Adder Cell with 50% Improvement in Threshold Loss Problem"]. p. 1.
2. ^ "The Adder". p. 4
3. ^ [http://arxiv.org/ftp/arxiv/papers/1201/1201.1966.pdf "Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate"]. p. 1