The Ubicom 3k supports 8 threads, not 64. It supports 64 scheduling slots, which is a different thing.
Ooops, you're right. I didn't read carefully enough the first time. --DavidCary 07:53, 28 November 2005 (UTC)
Ideas for further information:
- When did these barrel processors first come out?
- How mainstream were they?
- What influenced their design?
- What other designs did they influence?
- If there are less total threads than the number that the barrel processor was built to deal with, what happens then?
- If there are more total threads than the number that the barrel processor was built to deal with, what happens then?
Ed Sanville 22:40, 3 October 2006 (UTC)
during a stall
The article currently claims
- In addition, if there are insufficient threads available to run, a barrel processor may not have anything useful to do during a stall.
This may be true, but isn't it also true for every other kind of processor? Is there any kind of processor that doesn't have this "problem"? --DavidCary 05:39, 20 December 2005 (UTC)
What should be done about this then? 188.8.131.52 13:49, 24 May 2006 (UTC)
"Cray T90 vs. Tera MTA: The Old Champ Faces a New Challenger" http://www.cs.ucsd.edu/users/carter/Papers/cug.html mentions that "The MTA keeps the context of up to 128 threads in hardware called streams ready to execute on the processor. It can switch context each cycle and so keeps the processor saturated. If one thread cannot execute (due, say, to an outstanding memory reference), then an instruction from a different ready thread is issued. Each thread can issue only once in 21 cycles. This means that a minimum of 21 threads is required to keep the processor saturated."
Is this a kind of barrel processor, since it takes such a long time after a thread executes one instruction before it's turn "rolls around" to execute the next 2 consecutive instruction? Or is this more like hyperthreading?
--184.108.40.206 05:49, 6 February 2006 (UTC)
- It looks like it's both; a 6x-ish hyperthreaded 21-barrel processor (what a bizarre set of numbers... must be more that are reserved for handling scheduling overhead). The tip off for a barrel processor is when there is no way to saturate a core with only one thread. 220.127.116.11 11:05, 15 September 2007 (UTC)
- All the threads must share cache and registry space
Maybe I'm completely misreading this part, but "registry space" seems to have no relevance in context whatsoever, and linking it to "Windows registry" is just stupid. Could this be something to do with registers? I can't think what. De-linking for now.
- Fair point to be made, but I am not sure what constructive outcome is to be achieved by casting aspersions. The article was unwikified for quite some time; I took the time to complete the wikification effort, and am unimpressed by your uncouth behaviour. Until you can make a valid point for why it should be de-linked, I will have to leave the link in place. Folajimi 12:47, 11 March 2006 (UTC)
- You're the one with uncouth behaviour. You obviously know nothing about the subject. Glad that anonymous users have some sense and not always vandals. 18.104.22.168 13:50, 24 May 2006 (UTC)
- Probably meant just "registers" but in my understand even that isn't correct... they are't "shared" in the sense that multiple barrels read and write to them at once; the are only "shared" in the sense that they are decoupled from particular barrels so that a barrel switch for a particular thread doesn't require a physical register shuffling. 22.214.171.124 11:08, 15 September 2007 (UTC)
- I'm pretty sure that's wrong, since the Propeller is multicore parallel, whereas a barrel processor is more like a revolver--every clock cycle (trigger pull) the processor switches threads (revolver cylinder rotates one round). The Propeller's cores each execute their own thread every single cycle. I'll remove the link for now. Patrick O'Leary (talk) 19:20, 5 September 2008 (UTC)
- Propeller only uses the barrel technique for main memory access, while having eight distinct processors (called cogs). The XMOS XS1 architecture, however, seems to be a modern-day barrel processor. It uses up to 8 threads per core with a 4 thread pipeline, giving an instruction rate of frequency/max(4,threads) per thread. 126.96.36.199 (talk) 02:14, 10 February 2010 (UTC)
The article says that the CDC PPUs had a 20 thread barrel. I'm pretty sure that it was 10 and this is backed up up by the reference manual that is referenced in the article. I'm changing it to 10. Theodore.norvell (talk) 13:20, 5 January 2009 (UTC)