Talk:CPUID

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Unnamed section #1[edit]

CPUID is not specific to Intel Architecture, but its used in other CPUs as well, for example ARM MPCore [1], Altera NIOS2 [2]. In general, any architectural that supports Linux SMP kernel, must be able to uniquely identify underlaying processor to the kernel.

This page should be updated to incorporate this.

--Asadzia 07:56, 26 March 2007 (UTC)

IMO, the list of manufacturer IDs (specifically Transmeta) should be on individual lines, as the 2nd id for Transmeta was hiding. I'm gonna change it, unless theres a good reason why it was done this way. 79.79.213.203 (talk) 19:47, 17 November 2010 (UTC)

Unnamed section #2[edit]

The first example code segfaults when I run it, compile with:

as -g cpuid.asm -o cpuid.o
ld  -dynamic-linker /lib64/ld-linux-x86-64.so.2 -lc cpuid.o -o cpuid

Is this my error or is the source incorrect? My assembly isn't great, but shouldn't there be a

movl $1, %eax
int  $0x80

Kobrien88 (talk) 03:16, 23 January 2011 (UTC)

With the assemble/link commands you are using, yes, you are correct (at least on Linux.) I went ahead and changed the code. Should work with no segfaults now. Kabure (talk) 01:36, 14 February 2011 (UTC)

What is the rationale behind using assembly language snippets in this article? As shown under "..other languages" CPUID can be easily called from within C. As the majority of the assembly is about bit shifting, masking and formatting I'd consider C (or maybe even pseudo code) far more readable and giving more information to the average reader. I nobody speaks up, I'd like to replace the programs for the cache information and the brand string with C or pseudo code snippets. Also I'd like to add new leaves, especially AMD specific ones. To what detail shall this happen? Just a short description of the contained information or the full bit mask description? --APritzel (talk) 14:02, 1 August 2011 (UTC)

Hi, I get segfaults under Linux with Intel Compiler with the code in this article titled with "Or, a generally useful C implementation that works on 32 and 64 bit setups". The code was compiled als follows: icc -O0 -g test.c -o test. No segfault without -O0. Any idea? Disassembly:

Dump of assembler code for function cpuid:
0x000000000040056c <cpuid+0>:   push   %rbp
0x000000000040056d <cpuid+1>:   mov    %rsp,%rbp
0x0000000000400570 <cpuid+4>:   sub    $0x50,%rsp
0x0000000000400574 <cpuid+8>:   mov    %rbx,-0x18(%rbp)
0x0000000000400578 <cpuid+12>:  mov    %edi,-0x10(%rbp)
0x000000000040057b <cpuid+15>:  mov    %rsi,-0x50(%rbp)
0x000000000040057f <cpuid+19>:  mov    %rdx,-0x48(%rbp)
0x0000000000400583 <cpuid+23>:  mov    %rcx,-0x40(%rbp)
0x0000000000400587 <cpuid+27>:  mov    %r8,-0x38(%rbp)
0x000000000040058b <cpuid+31>:  mov    -0x50(%rbp),%rax
0x000000000040058f <cpuid+35>:  mov    -0x10(%rbp),%edx
0x0000000000400592 <cpuid+38>:  mov    %edx,(%rax)
0x0000000000400594 <cpuid+40>:  mov    -0x50(%rbp),%rax
0x0000000000400598 <cpuid+44>:  mov    -0x48(%rbp),%rdx
0x000000000040059c <cpuid+48>:  mov    -0x40(%rbp),%rcx
0x00000000004005a0 <cpuid+52>:  mov    -0x38(%rbp),%rbx
0x00000000004005a4 <cpuid+56>:  mov    %rax,-0x30(%rbp)
0x00000000004005a8 <cpuid+60>:  mov    (%rax),%eax
0x00000000004005aa <cpuid+62>:  mov    %rcx,-0x28(%rbp)
0x00000000004005ae <cpuid+66>:  mov    %rdx,-0x20(%rbp)
0x00000000004005b2 <cpuid+70>:  mov    %ebx,%edi
0x00000000004005b4 <cpuid+72>:  cpuid
0x00000000004005b6 <cpuid+74>:  mov    %ebx,%esi
0x00000000004005b8 <cpuid+76>:  mov    %edi,%ebx
0x00000000004005ba <cpuid+78>:  mov    %edx,(%rbx)
0x00000000004005bc <cpuid+80>:  mov    -0x28(%rbp),%rdx
0x00000000004005c0 <cpuid+84>:  mov    %ecx,(%rdx)
0x00000000004005c2 <cpuid+86>:  mov    -0x20(%rbp),%rdx
0x00000000004005c6 <cpuid+90>:  mov    %esi,(%rdx)
0x00000000004005c8 <cpuid+92>:  mov    -0x30(%rbp),%rdx
0x00000000004005cc <cpuid+96>:  mov    %eax,(%rdx)
0x00000000004005ce <cpuid+98>:  mov    -0x18(%rbp),%rbx
0x00000000004005d2 <cpuid+102>: leaveq
0x00000000004005d3 <cpuid+103>: retq
End of assembler dump.

ECX is output-only?[edit]

There is nothing on the page (or to my knowledge anywhere else) which supports the assertion that the ECX register is ever involved in selecting a return value.

the value in the EAX register, and in some cases the ECX register, specifies what information to return

Accordingly I propose that the highlit phrase be struck from the article. Martin Kealey (talk) 04:01, 21 August 2013 (UTC)

Extended function msb[edit]

The article says "To obtain extended function information CPUID should be called with the second most significant bit of EAX set. To determine the highest extended function calling parameter, call CPUID with EAX = 80000000h." Isn't 0x80000000 setting the most significant bit, rather than the 2nd msb? 110.77.158.29 (talk) 06:54, 24 February 2014 (UTC)

CPUID for input EAX=4[edit]

Does useful stuff. Should be added. 188.27.81.64 (talk) 08:45, 10 July 2014 (UTC)

App note 485 gone[edit]

Even the removal notice thereof is gone from Intel's site, but the notice can still be read at http://web.archive.org/web/20130626034554/http://www.intel.com/content/dam/www/public/us/en/documents/application-notes/processor-identification-cpuid-instruction-note.pdf 188.27.81.64 (talk) 09:58, 10 July 2014 (UTC)

External links modified[edit]

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KVM manufacturer ID string[edit]

The KVM manufacturer ID string is only 9 characters long - should it not be 12? — Preceding unsigned comment added by Joe Glancy (talkcontribs) 17:50, 10 June 2016 (UTC)