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|This is the talk page for discussing improvements to the CPU cache article.|
|WikiProject Computing||(Rated C-class, Mid-importance)|
|CPU cache is a former featured article. Please see the links under Article milestones below for its original nomination page (for older articles, check the nomination archive) and why it was removed.|
|This article appeared on Wikipedia's Main Page as Today's featured article on January 7, 2005.|
|Current status: Former featured article|
|Version 0.5||(Rated C-class)|
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The article does not make mention of a stall, which is what occurs to program execution when a cache miss occurs. That is were the penalty is ultimately felt, because the program executes slower.
Also the article needs rewording. I'm a software developer, and still had a great deal of difficulty trying to follow along with the article. I wouldn't think it would be very useful to a lay-person in this state. It contains lots of good information; the sentences are just hard to follow. — Preceding unsigned comment added by Dan East (talk • contribs) 17:43, 6 January 2005 (UTC)
- Very disappointing to hear. If you can say anything about where you were having trouble following along, it might help me fix the article. Iain McClatchie 01:28, 7 Jan 2005 (UTC)
There was an apparent merger with the L1, L2, and L3 caches of a CPU. I would like it if there were sections depicting each or at least a section that explains them. — Preceding unsigned comment added by Laboye (talk • contribs) 14:49, 20 September 2006 (UTC)
I find it confusing that the same word (index) denotes both tags in the Tag SRAM and words in the Data SRAM. Index often denotes the part of address used for selecting the whole cache line (Addr[10:6]), which is not the same as the part used for addressing the Data SRAM (Addr[10:2]) as shown in the image.
Usually people draw the index field connected to a decoder which selects the line. The relevant portion of the line is finally extracted by an additional decoder, which is addressed by the offset field of the address.
The detached organization in the image is also fine, but the words "index" in each line seem redundand and confusing.
Perhaps you could attribute Data SRAM entries as word 0, word 1, etc, and the Tag SRAM entries as tag 0, tag 1, etc? — Preceding unsigned comment added by 126.96.36.199 (talk • contribs) 10:47, 17 November 2008 (UTC
No mention of L0 cache?
How come this article has no mention of L0 cache? Various CPU's, including the Cyrix 686 mention an L0 "scratch-pad" cache, Qualcomm processors also include mention of L0 cache, as well as numerous research papers. I do not know enough to write an authoritative piece on it, but someone with more knowledge should definitely consider writing it.