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WikiProject Computing / Hardware (Rated B-class, Mid-importance)
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Former good article nominee DDR4 SDRAM was a Engineering and technology good articles nominee, but did not meet the good article criteria at the time. There are suggestions below for improving the article. Once these issues have been addressed, the article can be renominated. Editors may also seek a reassessment of the decision if they believe there was a mistake.
Article milestones
Date Process Result
September 12, 2008 Articles for deletion Merged
July 24, 2011 Good article nominee Not listed
Did You Know
Current status: Former good article nominee


The paragraphs cited with references 8 and 9 are plagiarized (copied and pasted) from the respective site. Phy1729 (talk) 18:40, 31 October 2010 (UTC)

I fixed this but it is still a very bad article. I think the fundamental problem is that DDR4 isn't a real thing yet, the specification won't be finalized until at least 2011 so we're basically talking about the efforts to create DDR4. And we're not even doing much of that, it's just a copypasta of tech news sites giving a variety of widely variable predictions on clockspeed, voltage, and how many years away it is without even talking about the current proposed design (which from some quick Googling seems to be an interesting new kind of point-to-point bus unlike previous SDRAM). Oh and hey it seems there's a better version of this article in the SDRAM article, where we deleted and merged this two years ago. If I'm not lazy I'll AfD again. Alereon (talk) 00:49, 25 November 2010 (UTC)
Note: redirected Jan 3 2011. FT2 (Talk | email) 09:56, 26 April 2011 (UTC)

GA nominee[edit]

DDR4 is now fabricated and a solid article can be written. Awaiting GA review. FT2 (Talk | email) 00:05, 29 April 2011 (UTC)

Thanks a lot for your hard work, this is a great article now! Alereon (talk) 10:05, 4 May 2011 (UTC)

Request for check of correct data on memory speeds[edit]

As with most DDR and SDRAM, the article has to carefully distinguish clock rates and data rates. I notice someone has edited the article replacing sourced data by unsourced data and MHz by MT/s. I've reverted this and checked it to source, but as I'm not an expert I would like to ask that someone checks my revert and that the data in the article is correct (and per source). I think it's correct. It's certainly per source.


Thanks! FT2 (Talk | email) 00:34, 5 May 2011 (UTC)


Nothing in the article about the physical aspects. Does DDR4 physically go in the same slots as DDR3? Regards, SunCreator (talk) 13:13, 26 June 2011 (UTC)

I don't think the physical aspects are finalized yet, but due to the extreme changes there will likely be no compatibility with DDR3, either physical or electrical. DDR3 and DDR2 used physically different slots, and yet many DDR3 memory controllers could also support DDR2 (for example, you can put an AMD Socket AM3 processor into a Socket AM2+ board with DDR2 and it will work, though not vice versa). I tried some Googling, but it's really hard to find good results because of the old GDDR4 memory, which was often just called DDR4. Alereon (talk) 10:02, 22 July 2011 (UTC)

The AM3 CPUs were a special case. They had two memory controllers, one for DDR3 and one for DDR2. That was why they supported DDR2 and DDR3, not because their DDR3 controller supported DDR2 memory. DDR4 and DDR3 will not be inter-compatible. Whether or not AMD will do something similar to their AM3 CPUs such as having their first CPUs to have DDR4 support also have a *legacy* DDR3 controller for DDR3 support is undetermined as far as I know.

  • This is not true. AMD had a heavy involvement in both early DDR2 and DDR3 development (this was shortly just after Intel RAMBUS stint and during time when Intel focused on FB-DIMMS/serial memory). With having IMC on the chip limiting upgrade path options they pretty much steered the standard to a solution that enabled same controller to support both DDR3 and DDR2 with minimal overhead. Several companies took advantage of that during DDR2-DDR3 transition, AMD being only the most prominent one.
  • Such path firstly was not needed business wise any more (all competitors use IMCs these days). Secondarily the DDR2 physical interface is trully legacy by this age and compatibility break was pretty much required for DDR4 generation. (talk) 13:20, 10 May 2014 (UTC)

Mhz, MT/s & Mbps[edit] The image is in MT/s actually. MT/s is twice that of Mhz due to Double Date Rate or DDR.

Quote from DDR3 wiki: "DDR3 modules can transfer data at a rate of 800–2133 MT/s using both rising and falling edges of a 400–1066 MHz I/O clock. Sometimes, a vendor may misleadingly advertise the I/O clock rate by labeling the MT/s as MHz."

Alternatively, you can open up a CPU-z. A DDR3-1333 (or 1333MT/s) will run at 665MHz clock.

It is a totally different story for Mbps, thus I left this sentence intact as i'm not sure. "The minimum clock speed of 2133 MT/s was said to be due to progress made in DDR3 speeds which, being likely to reach 2133 Mb/s" but i suspect something wrong with the 2133 Mb/s.

Quote from "" "The new DDR4 DRAM module can achieve data transfer rates of 2133Gb/s" "1.35V and 1.5V DDR3 DRAM at an equivalent 30nm-class process technology, with speeds of up to 1.6Gb/s." (talk) 15:20, 12 September 2011 (UTC)


JEDEC has not yet confirm Point-to-point with DDR4, can someone remove it from the article? ty. (talk) 15:20, 12 September 2011 (UTC)

I don't think that this should be removed as the change to a point-to-point bus is adequately sourced. NOTHING is truly finalized until the JEDEC releases final DDR4 specifications. Alereon (talk) 10:20, 17 September 2011 (UTC)

Cites are messed up[edit]

Colinstu (talk) 20:28, 20 February 2012 (UTC)

What's an MT?[edit]

The article doesn't explain or link to the definition of an "MT" or an "MT/s." If I had to guess, I'd think "mega-transfers" and "mega-transfers per second." Would someone who can confirm this please correct the article? -LesPaul75talk 17:40, 9 May 2012 (UTC)

fixed Colinstu (talk) 04:05, 9 June 2012 (UTC)

Multidrop DDR4[edit]

According to Samsung's presentation GSPS001 at IDF 2012, DDR4 will support up to 3 DIMMs per channel, at a cost in clock speed. See pages 10, 24 (the "24 ranks per channel"), and especially the figure on the right of p.15, which shows limits of 3200, 2133, and 1333 MT/s with 1, 2 and 3 DIMMs/channel. It appears that LR-DIMM techniques are in use (not clear if this is all DIMMs or just server DIMMs), with buffers on the edge of the DIMM for high density DIMMs.

It might be that only one DIMM/ch is permitted with unbuffered DIMMs, but I think this presentation throws the general statement into serious question. Unfortunately I don't have a source specific enough to really nail down the true answer. (Feel free to weaken "Dispute" to "Dubious" if someone thinks that's more appropriate.) (talk) 01:17, 14 September 2012 (UTC)

DDR4 command encoding[edit]

Anybody cares to enlighten us about the meaning and function of the shorts in the "DDR4 command encoding" table? CS; BGn, BAn; ACT; RAS; CAS; WE — Preceding unsigned comment added by Jangirke (talkcontribs) 03:23, 27 August 2014 (UTC)

Gigabyte vs. gibibyte[edit]

Hello, Fnagaton! Regarding my edit, I do agree that using "GB" instead of "GiB" is better and according to the Manual of Style (WP:COMPUNITS, in particular), but linking "GB" to Gibibyte is actually beneficial to the readers, as those are gibibytes in the sense of using powers of two. That's what I've referred to. Hope you agree. — Dsimic (talk | contribs) 13:52, 8 July 2015 (UTC)

It's not beneficial to link to gibibyte for the same reason it's not beneficial to show GiB or gibibyte. Fnagaton 14:10, 8 July 2015 (UTC)
Then what's your proposal for clarifying (briefly) that "GB" refers to 10243 instead of 10003 bytes? — Dsimic (talk | contribs) 14:26, 8 July 2015 (UTC)
Yes that's exactly the preferred method described in WP:MOSNUM. Disambiguation should be shown in bytes or bits, with clear indication of whether in binary or decimal base. An example: A 64 MB (64 × 10242byte) RAM chip. Fnagaton 14:33, 8 July 2015 (UTC)
After having a look at the Gigabyte article, the simplest solution is to link to Gigabyte instead, as it already contains an explanation of the "power of two" differences. Went ahead and edited the article that way, which should settle our slight disagreement. :) — Dsimic (talk | contribs) 14:46, 8 July 2015 (UTC)
The JEDEC standards for DDR4 memory use GB in the binary sense.[1] All of their memory standards use KB, MB and GB.
This section contains listings and definitions of a number of terms that are needed for a clear understanding of the standards as presented. Most of these terms have been developed within the semiconductor memory industry and are not covered by JEDEC Standard 100. They are, however, not in conflict with this standard which contains all JEDEC approved definitions.
2.5.4 – K When describing the storage capacity of a memory device the quantity K=1024 is used.
2.5.5 – M When describing the storage capacity of a memory device, the quantity M=2 exp 20 or 1024 K is used.
SWTPC6800 (talk) 20:37, 8 July 2015 (UTC)
That's fine, of course, but the thing is that we can't assume the readers' awareness of the use of "GB" in a binary sense. — Dsimic (talk | contribs) 23:48, 8 July 2015 (UTC)

Module table contents[edit]

The module table that was added skips 3 speeds which are listed in the JEDEC module document because those speeds are not listed in the device specification (JESD79-4A). Not being in JESD79-4A means that the respective CAS latencies cannot be supplied (given that the table comprises information from both sources). It is an interesting question whether to put them into the table with some missing information or to skip them (as was done for the original addition of the table). The missing speeds are 2666, 2933, and 3200. — Preceding unsigned comment added by (talk) 02:50, 9 December 2015 (UTC)

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