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Does anybody have the Programmer's Reference Guide
It's been over 30 years since I've worked on a 200 series computer, so some of this may be foggy.
Address mode 2 had no index registers, the entire 12 bits was the operand address giving a 4,096 character address range.
Address mode 3 had a 15 bit address allowing 32,768 bytes to be addressed. The remaining high order 3 bits were the address modifiers. 0 meant no modification and 1-6 meant the address was offset by index registers 1 to 6. Modifier value 7 meant the address was an indirect address, in other words it was the address of a 3 character location in memory which contained the actual address of the operand.
Address mode 4 (this is fuzzy). The address portion was 18 bits and the remaining bits indicated one of 2 sets of 16 index registers or an indirect address.
Change Sequence Mode swapped the instruction register contents with the address contained in the Change Sequence register. This was usually used with instruction trapping mode which caused a sequence swap when an instruction with an item-marked op-code was encountered. Was there an actual CSM instruction, or was trapping the only way to do this?
The system also had a basic interrupt structure and supported basic multi-programming operation. 188.8.131.52 15:37, 11 May 2007 (UTC)
The MAT (move and translate) and MIT (move item and translate) Have a third address made up of 2 variant characters following the B address. The variant characters and the character being translated form a third addres to fetch the character from the translate table. Page 8-77 and 8-80 of the Programmers Reference Manual.
In two character address mode the high order address bits of AAR amd BAR are retained when you switched down. The 4,096 character address range is with in the bank retained in the address registers AAR amd BAR. A good way of compacting code.
The SW (set word mark) and SI (set item mark instruction) instruction needed no punctuation (word mark on next instruction) to terminate their retreival. The first instruction of the boot strap is a SW. One anoying feature of the H200 is that the boot started in what ever address mode the processor was in. The normal boot strap required it to be in 2 character mode.
I found a Programmers Referance Manual at http://www.bitsavers.org/pdf/honeywell/h200/WP8593_Mod_200_1200_2200_pgmg_Dec65.pdf
In 4 character address mode there are 30 index registers. Registers 16 - 30 are relative the barricade register.
Steamerandy (talk) 09:41, 17 May 2012 (UTC) The 4 char mode on early machines was 18 bits, but later machines (3200 and 2070 and 2xxx derivitives, 42/8200) had 19 bits for half-meg ram and upper bits: 0 was raw, one value was indirect, and the rest were divided in two, indexing with or without relocation turned on, for O/S support of applications. (DGPickett@aol.com)
The 1250 and 2200 models would have corosponding instruction as programs were mostly upword compatability. I only worked on the H200 model. But Costa Mesa school district had a H3200. We shared code with them. I wrote an operatoring system for the H200. It was designed for streamlining student jobs. Basically a JCL reader that used an illigal punch code in column 1. I read cards in column binary looking for JCL cards having all rows in column 1 punched. Used MAT, Move And Translate, instruction to convert rest of card that was in column binary 12 bit. ard imsge to 6 bit character codes. Modified all compilers to run from disk. The illigal column 1 punch code prevented one job reading the next as data. I also wrote a file system for disk. Mainly so all compilers could be on the same disk. FORTRAN used relative load calls that in my loader were translated to relative file in the directory. FORTRAN was installed so its load segments matched up to the disk folder file order. That allowed the collage to have open computer labs instead of specific language labs.
The collage replaced the H200 with a DEC-SYSTEM-10. I later went to work for DEC as a software specialist. I do not know if my OS went any ware besides the collage. I was a student when I initially wrote that OS. The data center gave me operator job but I functioned as a systems programmar. My OS eliminated the need for a computer operator. Working for the data center I added console features for running programs from disk and extended the JCL for saving compilations to files on disk. Also a manual swap feature that allowed a running job to be save to disk and restated.
On another note:
I believe Easycoder and other compilers optionally output self loading object file. It was an option in the control card. Each translation system used a control or option card. That I am sure of because I had to generate the card image from my JCL language. I modified the FORYRAN, COBOL compilers and EASYCODER assembler to use a card image I created in memory. We had source code for all of the language translators. The program loader was integrated into my operatoring system. Load records were on cards or card images on tape or disk. The first few column were a sequence number that on disk I replaced with the next record address. Load files on disk were not sequential but linked so a single buffer could by used with minimal rotational latency.Steamerandy (talk) 00:35, 23 June 2017 (UTC)