Talk:Instruction pipelining

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"Every Microprocessor??"[edit]

"Every microprocessor manufactured today uses at least 2 stages of pipeline. (The Atmel AVR and the PIC microcontroller each have a 2 stage pipeline). Intel Pentium 4 processors have 20 stage pipelines."

I don't like the absolute word "Every" in that sentence. To my knowledge, the 8051 and its derivatives are usually not pipelined, and the 8051 is still one of the most popular micro-controllers around. At very least, the speed of the 8051 is not dependent on conditional branches like the PIC, or ARM. -- (talk) 13:30, 5 May 2008 (UTC)

I agree that the 8051 is still popular. However, (a) the original non-pipelined 8051s are no longer manufactured -- Intel no longer manufactures any 8051 (neither does AMD[1]), and (b) I've been told that the Dallas/Maxim 8051 derivatives are pipelined -- that's why they are advertised as "12 times faster"[2]. Does anyone still manufacture non-pipelined CPUs? -- (talk) 20:07, 1 December 2008 (UTC)
Are you saying that for example the NXP P80C554SFBD, which takes 6 clocks per CPU cycle, is pipelined? I think not. --Bdijkstra (talk) 20:12, 25 May 2012 (UTC)

Does slowest step imply full set of sub-instructions?[edit]

" This allows the computer's control circuitry to issue instructions at the processing rate of the slowest step" Here it's implying that the slowest step encapsulates all the sub-instructions and is generic for all instructions in the architecture, I find the word "slow" to be in need of a better term. Perhaps issuing instructions at the processing rate of the entire sub-instruction set of the pipeline is more clear? ChazZeromus (talk) 01:09, 23 April 2011 (UTC)

The term "sub-instruction" is ambiguous and not mentioned in the article. I assume that you mean the operation performed by a single stage. The slowest step can be defined without referring to sub-instructions and is simply the slowest step of all the potential steps that can be performed at any stage. So it encompasses (not encapsulates) all stages (not sub-instructions) and is general (not generic). The terms "issuing" and "processing rate" of your suggestion are ambiguous and not mentioned in the article (any more). --Bdijkstra (talk) 21:33, 25 May 2012 (UTC)

Why does "superpipelined" redirect here?[edit]

Not used or defined in article. (talk) 17:28, 26 August 2014 (UTC)

Note that page's history. It was a separate article until 2005, when it was redirected here. I take it that "superpipelining" is a follow-on technique to pipelining, in which the most time-consuming individual stages are replaced by multiple stages, each of which is shorter in duration and presumably can be executed in parallel. Spike-from-NH (talk) 21:23, 26 August 2014 (UTC)

Negation missing?[edit]

While reading the page, I saw this sentence:

It therefore allows faster CPU throughput (the number of instructions that can be executed in a unit of time) than would otherwise be possible at a given clock rate.

Shouldn't that be "wouldn't otherwise be possible"? Seems confusing to me. — Preceding unsigned comment added by V shashenko (talkcontribs) 08:32, 21 June 2016 (UTC)

Hello! The sentence is fine, it compares the pipelined (first part of the sentence) and non-pipelined (the second part) instruction throughputs. Hopefully, this will make it more clear. — Dsimic (talk | contribs) 08:48, 21 June 2016 (UTC)