Talk:Minimal instruction set computer

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multiple not minimal, as in multiple instead of reduced instruction set.

OK, there's now a brief mention of "multiple instruction set computer". There seem to be enough references for "minimal instruction set computer" to establish enough notability for this Wikipedia article about them. Are there enough references for "multiple instruction set computer" to establish enough notability to start a Wikipedia article about them? --DavidCary (talk) 05:42, 6 June 2014 (UTC)
That looks like enough references to me. Bubba73 You talkin' to me? 17:19, 6 June 2014 (UTC)

So, the main picture of the page is a diagram of an instruction pipeline, but the page clearly says "Instruction pipelines, branch prediction, out-of-order execution, register renaming and speculative execution broadly exclude a CPU from being classified as a MISC architecture system." — Preceding unsigned comment added by Adam.gausmann (talkcontribs) 23:44, 11 August 2016 (UTC)


How can a processor, the INMOS Transputer, with its *hundreds* of instructions, at all be considered MISC?

Likewise, ILP measurements on MISC architectures seems to explicitly avoid the use of macro-op fusion, where an instruction decoder recognizes patterns of instructions and operates them in parallel. This blurs the distinction between having "multiple instructions run at once" and "supporting a large set of insructions", but MISC has always been about the programmer/hardware interface (just like RISC), *not* about core implementation. Citation definitely needed for that. — Preceding unsigned comment added by 173.11.86.22 (talk) 03:52, 5 April 2017 (UTC)