Talk:Minimal instruction set computer

From Wikipedia, the free encyclopedia
Jump to: navigation, search
WikiProject Computing (Rated Stub-class)
WikiProject icon This article is within the scope of WikiProject Computing, a collaborative effort to improve the coverage of computers, computing, and information technology on Wikipedia. If you would like to participate, please visit the project page, where you can join the discussion and see a list of open tasks.
Stub-Class article Stub  This article has been rated as Stub-Class on the project's quality scale.
 ???  This article has not yet received a rating on the project's importance scale.
Note icon
This article has been automatically rated by a bot or other tool as Stub-Class because it uses a stub template. Please ensure the assessment is correct before removing the |auto= parameter.

multiple not minimal, as in multiple instead of reduced instruction set.

OK, there's now a brief mention of "multiple instruction set computer". There seem to be enough references for "minimal instruction set computer" to establish enough notability for this Wikipedia article about them. Are there enough references for "multiple instruction set computer" to establish enough notability to start a Wikipedia article about them? --DavidCary (talk) 05:42, 6 June 2014 (UTC)
That looks like enough references to me. Bubba73 You talkin' to me? 17:19, 6 June 2014 (UTC)

So, the main picture of the page is a diagram of an instruction pipeline, but the page clearly says "Instruction pipelines, branch prediction, out-of-order execution, register renaming and speculative execution broadly exclude a CPU from being classified as a MISC architecture system." — Preceding unsigned comment added by Adam.gausmann (talkcontribs) 23:44, 11 August 2016 (UTC)

How can a processor, the INMOS Transputer, with its *hundreds* of instructions, at all be considered MISC?

Likewise, ILP measurements on MISC architectures seems to explicitly avoid the use of macro-op fusion, where an instruction decoder recognizes patterns of instructions and operates them in parallel. This blurs the distinction between having "multiple instructions run at once" and "supporting a large set of insructions", but MISC has always been about the programmer/hardware interface (just like RISC), *not* about core implementation. Citation definitely needed for that. — Preceding unsigned comment added by (talk) 03:52, 5 April 2017 (UTC)