|WikiProject Computing||(Rated Start-class, Mid-importance)|
>Some NMIs may be masked, but only by using proprietary methods specific to the particular NMI.
Actually, on AT and compatible chipsets NMI can be disabled if bit 7 of port 70h is high. This is well documented, and a source is here. NMI means the interrupt cannot be disabled by the CLI instruction or by the PIC, there are still other ways to disable it. System86 (talk) 00:13, 30 January 2008 (UTC)
Minimum timing between NMIs?
ChazZeromus (talk) 01:47, 4 August 2009 (UTC) If your talking about x86 architecture, I do believe it simply task switches. Depending on the type of gate that the interrupt is associated with, a successful forced task switch will take place if operating in protected mode. It's somewhere in the Systems Programming manual from Intel.