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Chronological ordering of SPARC microprocessor specifications[edit]

Is there any reason why it isn't ordered chronologically? I would like to order it chronologically if there is no reason why it shouldn't be. Rilak (talk) 09:13, 4 May 2009 (UTC)

It's vaguely chronological, but with some clustering of related series of processors. If we go for strict chronology, perhaps we should consider breaking it up into sub tables to illustrate the broad families? (eg. something like V7, SuperSPARC, hyperSPARC, MicroSPARC, TurboSPARC, UltraSPARC, SPARC64, UltraSPARC T?). Letdorf (talk) 11:08, 4 May 2009 (UTC).
Yeah, breaking it up by ISA version is better idea as its a confusing at the moment. We don't have anything on V7 SPARCs though, which needs to be fixed. Perhaps this would be a good opportunity? Rilak (talk) 11:37, 4 May 2009 (UTC)
Yes, I thought about listing the various V7 implementations, but there were a number of them, most were very similar, the IUs and FPUs were discrete chips and details like die size and transistor count are hard to come by. Two interesting implementations worth noting though were the Panasonic MN10501 KAP used by Solbourne and the Bipolar Integrated Technology B5000. I believe these were both V7-compliant. Letdorf (talk) 12:40, 4 May 2009 (UTC).
My understanding is that the B5000 and MN10501 were not very popular. While information about the B5000 is easy to get (from the Hot Chips archive), the MN10501 doesn't seem to have been mentioned at all. The SPARC chip sets made by Cypress Semiconductor and LSI Logic were the most commonly used, so perhaps they should have higher priority. Fujitsu, Texas Instruments and Weitek also made SPARC V7 parts. I think it is possible to obtain information about most of them from archived news articles, for example, this [ article] has a bit about the first SPARC. Rilak (talk) 06:16, 5 May 2009 (UTC)
Another good reference is the Sun Hardware Reference which lists the CPUs used in older Sun systems. The B5000 and the KAP aren't notable for their popularity, but they were interesting for being an ECL implementation, and an early example of a SPARC-compatible chip developed without the participation of (indeed, in competition with) Sun, respectively. There's some mention of the KAP here and here, and I think this paper is about the KAP too. Letdorf (talk) 10:01, 5 May 2009 (UTC).
Interesting links. I looked for the KAP a while ago and didn't think anything. In regards to the links, I don't think there is anything that isn't in the list of SPARC V7s from SPARC International. I haven't looked into them yet, except for the CY7C601 chip set. We need a draft page somewhere to work on this. Rilak (talk) 12:24, 5 May 2009 (UTC)


There is a claim that some Fujitsu SPARC processors have hardware implementations of decimal floating point. I don't see a reference for this, though, so I looked here. Does anyone here know about that? Gah4 (talk) 20:52, 18 September 2017 (UTC)

I presume you have seen Decimal_floating_point ("Fujitsu also has Sparc processors with DFP in hardware").
I have never seen any definitive reference to DFP op-codes for any Fujitsu SPARC processor, but given Fujitsu ported their BS2000/OSD mainframe operating system (inherited from Siemens) to SPARC in the early 2000s, it would not be totally surprising to find they had either customised cores, or DFP co-processors (using the traditional SPARC co-processor interface) lurking in their SX series mainframes somewhere - Fujitsu SX mainframes might be a good place to start looking.
Secondly, the SPARC64V was loosely based on the 1999 Fujitsu GS8900 (non-SPARC) mainframe processor, so *just might* therefore have some poorly-documented DFP capabilities hidden away somewhere, perhaps only available when loaded with "mainframe" microcode.
The (Fujitsu) MB86900, microSPARC-II and TurboSPARC did not have DFP in hardware (except possibly using an external co-processor).
Good luck with your search, remember to post any interesting results back here. Shelldozer (talk) 11:08, 19 September 2017 (UTC)

Soft-Cores versus Concrete Implementations[edit]

Not too happy that "LEON4" is in the main table, with most of the fields blanked out (because it is a ***configurable*** VHDL "soft-core" rather than an actual microprocessor). Replacing it with a concrete implementation, eg: Cobham Gaisler GR740, where the data-fields *can* be filled-in, sounds like a better way to go.

Perhaps this page should have a separate summary paragraph listing the known SPARC soft-cores: OpenSPARC T1/T2; ERC32; the LEON series (with a link to the LEON Wikipedia article for the gory details); and so on. Shelldozer (talk) 12:34, 19 September 2017 (UTC)


Alternative suggestion: could use eg: LEON4 or LEON3 as the generic-/code-name ("micro-architectural name"), and eg: GR740 or GR712RC as the specific model name ("concrete implementation name"). Shelldozer (talk) 12:34, 19 September 2017 (UTC)
I have adopted the alternative suggestion, and updated the main article page accordingy. Shelldozer (talk) 14:32, 19 September 2017 (UTC)

Infrant IT3103 and IT3107[edit]

As concrete (and heavily productized!) examples of embedded SPARC, it would be useful if we could dig up more information on the Infrant Technologies' IT3103 and IT3107 LEON2-based SPARC processors used in the Infrant (later NetGear) ReadyNAS NV1 boxes starting from 2005; eg configured on-chip cache sizes, process-node/die-size, power (W), no. I/O pins. We can surmise some details from the non-configurable parts of LEON2 (ie: threads/cores, arch. version) and some from the press releases and historical product brochures (ie: year 2005).

Shelldozer (talk) 14:03, 19 September 2017 (UTC)