Talk:Segment descriptor

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Removed unsourced text[edit]

I removed this text: "The memory is subdivided into segments. A segment in the x86 architecture can be from 1 byte to 4Gbyte long. It can start at any base address in memory. Each segment has a segment descriptor associated with it." It's unsourced, and per this discussion there is a significant concern about copyvios in unsourced material from the India Education Program. Mike Christie (talk - contribs - library) 01:16, 28 October 2011 (UTC)

Look out for possible copyright violations in this article[edit]

This article has been found to be edited by students of the Wikipedia:India Education Program project as part of their (still ongoing) course-work. Unfortunately, many of the edits in this program so far have been identified as plain copy-jobs from books and online resources and therefore had to be reverted. See the India Education Program talk page for details. In order to maintain the WP standards and policies, let's all have a careful eye on this and other related articles to ensure that no material violating copyrights remains in here. --Matthiaspaul (talk) 12:51, 31 October 2011 (UTC)

Section moved from article[edit]

I've moved the following text here from the article as it was almost completely unsourced; it also has some formatting problems which should be fixed if it's to be returned. I've enclosed it in a collapse template as it contains section headings. See WT:IEP for an explanation of the reasons for this proactive removal of information. Mike Christie (talk - contribs - library) 00:03, 1 November 2011 (UTC)

Extended content

Types of descriptors[edit]

A logical address in Intel x86 consists of a segment selector and an offset. The most significant 16 bits of the segment selector defines the address of the segment descriptor, which is stored either in the Global Descriptor Table (GDT) or Local Descriptor Table (LDT). The description details mainly include the memory segment's first byte in linear address (Base), size (Limit) and Type (Bovet & Cesati, 2000, p. 36 - 41).

Types of Segment Descriptor Table:[edit]

Segment descriptors are stored in descriptor tables which are located in memory. The descriptor table is an array of 8K descriptors i.e. there are 8K descriptors in a descriptor table. All the segments used in the system are defined by the descriptor tables. There are three types of descriptor tables as follows:

1. Global Descriptor Table (GDT) :[edit]

It contains descriptors that are possibly available to all tasks in the system.

2. Local Descriptor Table (LDT) :[edit]

It contains descriptors associated with a given task. There may exist separate LDT for each task. For a task to access a segment, it is important that its segment descriptor should exist in either the current LDT or the GDT. The LDT register pointing to the LDT, can only be changed with LDTR instruction or by a task switch. Task Switch: Task State Segment (TSS) contains copies of all registers and flags, the selector for the task’s LDT and a link to the task state segment of previously executing task. Descriptors for the TSS are stored in GDT where they can be accessed by the operating system during a task switch

3. Interrupt Descriptor Table (IDT) :[edit]

It contains descriptors that point up to 256 ISRs location. IDT is an interrupt vector table in which each interrupt vector is a descriptor. Each interrupt requires 6 bytes. It stores task gates, interrupt gates and trap gates. It has 24-bit base address and a 16-bit limit register in CPU. The IDT entries are referred to by using INT instruction or exception or external interrupts This table can be located anywhere in the memory. When exception or interrupt occurs, its type is multiplied by 8 and added to the IDT base address in the IDT register. The result is a pointer to a gate descriptor in IDT.

Segment Descriptor Table Register :[edit]

Each of the above three types of the tables has a register associated with it:

             GDT           GDT Register  (GDTR)                  48
             LDT           LDT Register  (LDTR)                  16
             IDT           IDT Register  (IDTR)                  48

Instructions for Segment Descriptor Table:[edit]

      INSTRUCTION                FUNCTION
         LGDT        Loads the base and the limit of the GDT
         LLDT        Loads the base and the limit of the LDT
         LIDT        Loads the base and the limit of the IDT
         SGDT        Stores the contents of the GDTR into a specified destination address
         SLDT        Stores the contents of the LDTR into a specified destination address
         SIDT        Stores the contents of the IDTR into a specified destination address

Descriptor Selection:[edit]

A 16-bit segment register stores a 16-bit selector. It points to a segment descriptor in GDT or in LDT.

Bit specification:[edit]

1. Upper 13 bits:

    The upper 13 bits of a selector points to one of the 8192  descriptors in the descriptor table. 

2. Bit T1 (bit 2):

    It selects the GDT or LDT depending upon its value.
                T1=1    LDT
                T1=0    GDT

3. Requestor Privilege Level (RPL):

    It indicates the privilege level of the task which is requesting the memory access.

The three types mentioned above are memory arrays of variable length. They have size in the range 8 bytes (single descriptor) to 64 kbytes (8192 descriptors, 8 bytes each). The upper 13 bytes of a selector are used as an index into the descriptor table.

Access of Operand Using GDT :[edit]

 DS                The operand in memory is accessed in DS. Its upper 13 bits point to the descriptor.
 EIP            It contains offset of the  accessed operand
 DESCRIPTOR     Descriptor in GDT stores the base address of  the data segment.
 GDTR           It contains base address of the GDT.


Access of Operand Using GDT :[edit]

The LDT is used for a particular task. But it can be shared between the tasks as well. GDT contains a descriptor pointing to the base of the LDT. The register LDTR points to the LDT descriptor within the GDT. A LDT descriptor copy is stored in 64-bit register in CPU. (fig)