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SystemC provides hardware-oriented constructs within the context of C++ as a class library implemented in standard C++. Its use spans design and verification from concept to implementation in hardware and software. SystemC provides an interoperable modeling platform which enables the development and exchange of very fast system-level C++ models. It also provides a stable platform for development of system-level tools.

The Open SystemC Initiative (OSCI) is an independent not-for-profit organization composed of a broad range of companies, universities and individuals dedicated to supporting and advancing SystemC as an open source standard for system-level design.

find more details on [1]


SystemC traces its origins to work on Scenic programming language described in a DAC 1997 paper: Stan Y. Liao, Steven W. K. Tjiang, Rajesh K. Gupta: An Efficient Implementation of Reactivity for Modeling Hardware in the Scenic Design Environment. DAC 1997: 70-75


Article says,

The performance of this simulation kernel is not to be compared with that of commercial VHDL/Verilog simulators designed to simulate RTL level designs at the present.

Why are they not to be compared? Which one is better? (talk) 16:52, 19 September 2008 (UTC)

To paraphrase the first sentence of paragraph 4 'SystemC (is similar) to VHDL and Verilog, but (is similar) ...' I don't understand what that sentence is trying to say. Bread2u (talk) 17:47, 5 October 2009 (UTC)


"SystemC is applied to system-level modeling,[...]"

What is system-level modeling and what does it mean when something is applied to it? Thanks, --Abdull (talk) 19:47, 29 January 2010 (UTC)

Formal semantics[edit]

As far as I can see, SystemC lacks a formal semantics. The article states that "The LRM provides the definitive statement of the semantics of SystemC". The LRM is not avaiable to me, so I have a question at the bottom here.

In [1] I read:

"In this article, a denotational definition of synchronous subset of SystemC is proposed. The subset treated includes modules, processes, threads, wait statement, ports and signals. We propose formal model for System C delta delay. Also, we give a complete semantic definition for the language’s two-phase scheduler. The proposed semantic can constitute a base for validating the equivalence of synchronous HDL subsets."

In [2] I read:

"In 2009, OSCI developed a User Guide and LRM for the SystemC-AMS 1.0 standard. It defines the execution semantics and extensions to SystemC constructs (classes, interfaces, analog kernel and modeling of continuous-time analysis) for IP modeling of embedded analog/mixed signal systems at system-level, analog behavioral and netlist level."

And in [3] I read:

"Since SystemC has no formal semantics, this includes a careful encoding of the SystemC scheduler, which has both synchronous and asynchronous features, and a notion of time."

To me it seems like it would be fair to add something in the SystemC article that the basic language does not have any formal sematics. However, work has been done to define formal semantics for subsets of the language. Would this in any way contradict the LRM?

Øyvind Teig (talk) 10:33, 16 April 2012 (UTC)

[1] - "Formal Semantics of Synchronous SystemC", Ashraf Salem, Computer & Systems Eng. Dept. Ain Shams University (2003)

[2] - System-Level Design using SystemC, Miltos Grammatikakis, TEI of Crete

[3] - A SystemC/TLM semantics in Promela and its possible applications, Claus Traulsen1 (Verimag, Centre ´equation)