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In electronics design, tape-out or tapeout is the final result of the design process for integrated circuits or printed circuit boards before they are sent for manufacturing. The tapeout is specifically the point at which the graphic for the photomask of the circuit is sent to the fabrication facility. A synonym used at IBM is RIT (release interface tape). They differentiate between RIT-A for the non-metallic structures and RIT-B for the metal layers.
Historically, the term references the early days of printed circuit design, when the enlarged (for higher precision) "artwork" for the photomask was manually "taped out" using black line tape (commonly Bishop Graphics crepe). In the post-war era of the 1940-50s, the techniques developed for rapid and low-cost circuit reproduction evolved to photographically replicated 2D manufacturing. The verb "to tapeout" was already widely used for the process and adopted for transistor fabrication which evolved to full integrated-circuit approaches.
The process advanced to adhesive-backed die cut elements on sheets of PET film (rubylith) wherein a dimensionally stable mylar layer was loosely adhered to a red layer which was selectively removed (high-resolution monochrome photographic film of that era had optimal sensitivity to the blue end of the spectrum - the red mask was translucent to humans but opaque to film). Initially rubylith was manually separated according to the engineers design parameters, and later automated via diamond-tip equipped x-y drafting machines driven by NC tape systems or direct computer output at the initial stages of the CAD revolution. Subsequently, the artwork was photographically reduced. A similar process was used for early integrated circuits.
Some sources erroneously believe that the roots of the term can be traced back to the time when paper tape and later magnetic tape reels were loaded with the final electronic files used to create the photomask at the factory. However, the use of the term predates the widespread CAD usage of magnetic tape by decades.
The term tapeout currently is used to describe the creation of the photomask itself from the final approved electronic CAD file. Designers may use this term to refer to the writing of the final file to disk or CD and its subsequent transmission to the semiconductor foundry; however, in current practice the foundry will perform checks and make modifications to the mask design specific to the manufacturing process before actual tapeout. Optical proximity correction is an example of such an advanced mask modification; it corrects for the wave-like behavior of light when etching the nano scale features of the most modern integrated circuits.
A modern IC has to go through a long and complex design process before it is ready for tape-out. Many of the steps along the way use software tools collectively known as electronic design automation (EDA). The design must then go through a series of verification steps collectively known as "signoff" before it can be taped-out. Tape-out is usually a cause for celebration by everyone who worked on the project, followed by trepidation awaiting the first article, the first physical samples of a chip from the manufacturing facility (semiconductor foundry).
The weeks before the tapeout are categorized as sleepless nights in the parlance of IC Designers.
First tapeout is rarely the end of work for the design team. Most chips will go through a series of iterations, called "spins", in which errors are detected and fixed after testing the first article. Many different factors can cause a spin, including:
- The taped-out design fails final checks at the foundry due to problems manufacturing the design itself.
- The design is successfully fabricated, but the first article fails functionality tests.
At the University of California, Berkeley the tongue-in-cheek term "tape-in" was coined by Prof. John Wawrzynek to allude to iterative "internal tape-outs" in the spirit of agile design philosophy around 2010.
- Magee, Mike (14 July 1999). "What the Hell is… a tapeout?". The Register.
- Mays, Lonne (16 March 2006). "Follow Heuristic Guidelines To Make Surface-Mount PC-Board Footprints". Electronic Design. Archived from the original on 2011-08-11.
- Turley, Jim (2002). The Essential Guide To Semiconductors. Prentice Hall PTR. p. 37. ISBN 0-13-046404-X.