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In electronics and photonics design, tape-out or tapeout is the final result of the design process for integrated circuits or printed circuit boards before they are sent for manufacturing. The tapeout is specifically the point at which the graphic for the photomask of the circuit is sent to the fabrication facility.[1]


Historically, the term references the early days of printed circuit design, when the enlarged (for higher precision) "artwork" for the photomask was manually "taped out" using black line tape (commonly Bishop Graphics crepe) and also Rubylith sheets. In the post-war era of the 1940–50s, the techniques developed for rapid and low-cost circuit reproduction evolved to photographically replicated 2D manufacturing. The verb "to tapeout" was already widely used for the process and adopted for transistor fabrication, which evolved to full integrated-circuit approaches.[citation needed]

Procedures involved[edit]

The term tapeout currently is used to describe the creation of the photomask itself from the final approved electronic CAD file. Designers may use this term to refer to the writing of the final file to disk or CD and its subsequent transmission to the semiconductor foundry; however, in current practice the foundry will perform checks and make modifications to the mask design specific to the manufacturing process before actual tapeout. These modifications of the mask data include:[2]

  • Chip finishing which includes custom designations and structures to improve manufacturability of the layout. Examples of the latter are a seal ring and filler structures.
  • Producing a reticle layout with test patterns and alignment marks.[2]
  • Layout-to-mask preparation that enhances layout data with graphics operations and adjusts the data to mask production devices. This step includes resolution enhancement technologies (RET), such as optical proximity correction (OPC) which corrects for the wave-like behavior of light when etching the nano scale features of the most modern integrated circuits.[1]

Naming issues[edit]

Some sources erroneously believe that the roots of the term can be traced back to the time when paper tape and later magnetic tape reels were loaded with the final electronic files used to create the photomask at the factory.[1] However, the use of the term predates the widespread CAD usage of magnetic tape by decades.[citation needed]

At the University of California, Berkeley, the tongue-in-cheek term tape-in was coined by Professor John Wawrzynek to allude to iterative "internal tape-outs" in the spirit of agile design philosophy around 2010.[citation needed]

A synonym used at IBM is RIT (release interface tape). IBM differentiates between RIT-A for the non-metallic structures and RIT-B for the metal layers.[citation needed]


A modern IC has to go through a long and complex design process before it is ready for tape-out. Many of the steps along the way use software tools collectively known as electronic design automation (EDA). The design must then go through a series of verification steps collectively known as "signoff" before it can be taped-out. Tape-out is usually a cause for celebration by everyone who worked on the project, followed by trepidation awaiting the first article, the first physical samples of a chip from the manufacturing facility (semiconductor foundry).

First tapeout is rarely the end of work for the design team. Most chips will go through a series of iterations, called "spins", in which errors are detected and fixed after testing the first article. Many different factors can cause a spin, including:

  • The taped-out design fails final checks at the foundry due to problems manufacturing the design itself.
  • The design is successfully fabricated, but the first article fails functionality tests.

See also[edit]


  1. ^ a b c Magee, Mike (July 14, 1999). "What the Hell is… a tapeout?". The Register. Retrieved April 2, 2009.
  2. ^ a b J. Lienig, J. Scheible (2020). "Chap. 3.3: Mask Data: Layout Post Processing". Fundamentals of Layout Design for Electronic Circuits. Springer. pp. 102–110. doi:10.1007/978-3-030-39284-0. ISBN 978-3-030-39284-0. S2CID 215840278.