Tejas and Jayhawk
Tejas was a code name for Intel's microprocessor, which was to be a successor to the latest Pentium 4 with the Prescott core and was sometimes referred to as Pentium V. Jayhawk was a code name for its Xeon counterpart. The cancellation of the processors in May 2004 underscored Intel's historical transition of its focus on single-core processors to multi-core processors.
In early 2003, Intel showed Tejas and a plan to release it sometime in 2004, but put it off to 2005. Intel, however, canceled development on May 7, 2004. Analysts attribute these delays and cancellation to heat and power consumption problems due to their goal of reaching ever higher clock speeds, even when sacrificing work done per clock (and therefore performance per clock) in the process. This was already the case with Prescott and its mediocre performance increase over Northwood (not to mention heavy competition from AMD with their Athlon 64). Its changes were done to allow Prescott to attain >5 GHz clock speeds with ease, yet this was not possible due to physical limitations (heat generated, power consumed) at ambient temperatures. Tejas went even further ahead with this paradigm, with Intel targeting 10GHz clock speeds by 2011 back in July 2000 (Netburst was launched in November 2000). It was soon enough clear this represented a dead end.
This cancellation reflected Intel's intention to focus on dual-core chips for the Itanium platform. With respect to desktop processors, Intel's development efforts shifted to the Pentium M microarchitecture (itself a derivative of the P6 microarchitecture) used in the Centrino notebook platform, which offered greatly improved performance per watt consumed than offered by Prescott and other NetBurst designs. The outcome of these development efforts was the Intel Core processor line, and later the Intel Core 2 line, providing and building on the benefits of Pentium M and offering Intel's first native dual core products for desktops and laptops.
This defined the end for the Netburst architecture, with Core setting the foundation and path for power efficient architectures that followed along the Tick-Tock model.
Design and microarchitecture
Tejas and Jayhawk were to make several improvements on the Pentium 4's NetBurst microarchitecture. Tejas was originally to be built on a 90 nm process, later moving to a 65 nm process. The 90 nm version of the processor was reported to have 1 MB L2 cache, while the 65 nm chip would increase the cache to 2 MB. There was also to be a dual core version of Tejas called Cedarmill (or Cedar Mill depending on the source). This Cedarmill should not be confused with the 65 nm Cedar Mill-based Pentium 4, which appears to be what the codename was recycled for.
The trace cache capacity would likely have been increased, and the number of pipeline stages was increased to between 40 and 50 stages. There would have been an improved version of Hyper-Threading, as well as a new version of SSE, which was later backported to the Intel Core 2 series after Tejas' cancellation and named SSSE3. Tejas was slated to operate at frequencies of 7 GHz or higher. However, it's likely that Tejas wouldn't have had linear performance scaling, as it would on average have executed fewer instructions per clock cycle due to more pipeline bubbles from branch mispredicts and data cache misses. Also, it would have run hotter as well with a TDP much higher than the Prescott core of Pentium 4. The CPU was cancelled late in its development after it had reached its tapeout phase.
Initial claims reported early samples of single core 90 nm Tejas running at 2.8 GHz and rated for 150 W TDP on the LGA 775 socket, a notable increase over single core 90 nm Prescott (Pentium 4 521, 2.8 GHz, 84 W TDP) and higher than 90 nm dual core Smithfield (Pentium D 820, 2.8 GHz, 95 W TDP). In contrast, 65 nm dual core Core 2 Duo processors based on the Core microarchitecture had a maximum of 65 W TDP (E6850, 3.00 GHz) while being much more efficient with markedly higher performance per clock. However, the existence of engineering samples have been challenged and no source indicates that tape-out of Tejas ever existed - the sample shown in the Anandtech article  being a Prescott B0 ES. Most probably only thermal samples of Tejas were produced.
- Dutton, Paul. "Pentium V will launch with 64-bit Windows Elements". The Inquirer. Retrieved 31 March 2013.
- "ZDNet: The future of chips, Intel style". 2000-08-19. Archived from the original on 2000-08-19. Retrieved 2017-10-10.CS1 maint: BOT: original-url status unknown (link)
- Chip magicians at work: patching at 45nm
- Shimpi, Anand Lal. "Covert Ops in Taiwan - Intel Tejas & Socket 775 Unveiled". Retrieved 2016-12-01.
- "Intel® Pentium® 4 Processor 521 supporting HT Technology (1M Cache, 2.80 GHz, 800 MHz FSB) Specifications". Intel® ARK (Product Specs). Retrieved 2016-12-01.
- "Intel® Pentium® D Processor 820 (2M Cache, 2.80 GHz, 800 MHz FSB) Specifications". Intel® ARK (Product Specs). Retrieved 2016-12-01.
- "Intel® Core™2 Duo Processor E6850 (4M Cache, 3.00 GHz, 1333 MHz FSB) Specifications". Intel® ARK (Product Specs). Retrieved 2016-12-01.
- Samuel Demeulemeester (2018-09-11). "J'ai enfin résolu un mystère vieux de 15 ans : ce post de [anandtech] qui disait en janvier  avoir une photo de Tejas alors que mes sources affirmaient que Tejas n'avait jamais tape-out. J'ai retrouvé le CPU ... et c'est un Prescott B0 ES" [I finally solved a 15-years-old mystery: this anandtech post saying in January  to have a photograph of Tejas whereas my sources stated that Tejas was never tape-out. I found the CPU ... and it's a Prescott B0 ES.]. Retrieved 2018-09-12.