Template:Intel processor roadmap
This is a table with 11 columns × n rows, as derived from the graphic illustration worked up by the Commons Graphics Lab in a vertical format. The vertical format is used because the existing horizontal format is starting to require scrolling to display. This template version includes the complete P6 evolution (from its origin as the Pentium Pro microarchitecture) because of the added space afforded by the switch to vertical format.
However, updates to the existing template will require a bit more care, since tables are built row-by-row instead of column-by-column. <td rowspan=N> tags are used to expand cells beyond a single row, although that will require the editor to keep track of which cells and how many.
Columns are defined as:
- is the Atom family microarchitecture ("Atom TOCK")
- is the Atom processor codename ("Atom TICK")
- is the process/feature size, and formatted as "<td rowspan=2 style="border:1px solid black;'>[[22 nanometer|22 nm]]", for instance.
- is the desktop/laptop family microarchitecture ("x86 TOCK")
- is the desktop/laptop processor codename ("x86 TICK")
- is a spacer column
- is the (single-core) NetBurst processor name. It is reserved to insert the NetBurst microarchitecture only, and is used solely to add NetBurst development in parallel with P6 development. Columns 6–11 are not anticipated to require any further updating unless Intel adds another parallel/stub branch of microarchitectures. Hence many of the row definitions end with a spacer such as <td colspan=6>.
- is a spacer column with arrows to show the derivation of Prescott
- is the (hyperthreading) NetBurst processor name.
- is a spacer column with arrows to show the derivation of hyperthreading NetBurst processors
- is the (dual-core) NetBurst processor name. Because the dual-core NetBurst processor physically consisted of two dies on the same package, the graphical illustration displays this as a horizontal evolution.