# Temporal logic in finite-state verification

In finite-state verification, model checkers examine finite-state machines representing concurrent software systems looking for errors in design. Errors are defined as violations of requirements expressed as properties of the system. In the event that the finite-state machine fails to satisfy the property, a model checker is in some cases capable of producing a counterexample – an execution of the system demonstrating how the error occurs.

Property specifications are often written as Linear Temporal Logic (LTL) expressions. Once a requirement is expressed as an LTL formula, a model checker can automatically verify this property against the model.

## Example

One example of such a system requirement: Between the time an elevator is called at a floor and the time it opens its doors at that floor, the elevator can arrive at that floor at most twice.[1] The authors of "Patterns in Property Specification for Finite-State Verification" translate this requirement into the following LTL formula:

\begin{align}\Box((call \lor \Diamond open) \to & ((\lnot atfloor \lor \lnot open) ~\mathcal{U} \\ & (open \lor ((atfloor \land \lnot open) ~\mathcal{U}\\ & (open \lor ((\lnot atfloor \land \lnot open) ~\mathcal{U} \\ & (open \lor ((atfloor \land \lnot open) ~\mathcal{U} \\ & (open \lor (\lnot atfloor ~\mathcal{U}~ open)))))))))))\end{align}