Tick–tock model

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Tick–tock was a production model adopted in 2007 by chip manufacturer Intel. Under this model, every microarchitecture change (tock) was followed by a die shrink of the process technology (tick). It was replaced by the process–architecture–optimization model, which was announced in 2016 and is like a tick–tock cycle followed by an optimization phase. As a general engineering model, tick–tock is a model that refreshes one side of a binary system each release cycle.

History[edit]

Every "tick" represented a shrinking of the process technology of the previous microarchitecture (sometimes introducing new instructions, as with Broadwell, released in late 2014) and every "tock" designated a new microarchitecture.[1] These occurred roughly every year to 18 months.[2] In 2014, Intel created a "tock refresh" of a tock in the form of a smaller update to the microarchitecture[3] not considered a new generation in and of itself.

In March 2016, Intel announced in a Form 10-K report that it deprecated the tick–tock cycle in favor of a three-step process–architecture–optimization model, under which three generations of processors are produced under a single manufacturing process, with the third generation out of three focusing on optimization.[4] The first optimization of the Skylake architecture was Kaby Lake. Intel then announced a second optimization, Coffee Lake,[5] making a total of four generations at 14 nm.[6]

Roadmap[edit]

Pentium 4 / Core roadmap[edit]

Pentium 4 / Core roadmap
Change
(step)
Fabri­cation
process
Micro-
architecture
Code names
for step
Intel
Generation
Desktop
Intel
Generation
Xeon
Intel Microcode
shortcut(s)
Desktop/WS[7][8]
Intel Microcode
shortcut(s)
Xeon/Server
Release
date
Processors
8P/4P Server 4P/2P Server/WS Embedded Xeon 1P Xeon Enthusiast/WS Desktop Mobile
Tick
(new fabrica-
tion process
)
65 nm P6, NetBurst Yonah (P6),
Presler (NetBurst),
Cedar Mill (NetBurst)
1995-11-1 (P6),
2000-11-20 (Netburst)
Presler (NetBurst) Cedar Mill (NetBurst) Yonah (P6)
Tock
(new micro-
architecture
)
Core Merom[9] 2006-07-27[10][11] Tigerton Woodcrest
Clovertown
Kentsfield Conroe Merom
Tick 45 nm Penryn 2007-11-11[12] Dunnington Harpertown Yorkfield Wolfdale Penryn
Tock Nehalem Nehalem 1 NHM[13] 2008-11-17[14] Beckton Gainestown Lynnfield Bloomfield Lynnfield Clarksfield
Tick 32 nm Westmere 1 WSM[13] 2010-01-04[15][16] Westmere-EX Westmere-EP Gulftown Clarkdale Arrandale
Tock Sandy Bridge Sandy Bridge 2 1 SNB JKT (Jaketown) 2011-01-09[17] (Skipped)[18] Sandy Bridge-EP Gladden Sandy Bridge Sandy Bridge-E Sandy Bridge Sandy Bridge-M
Tick 22 nm[19] Ivy Bridge 3 2 IVB IVT (Ivytown) 2012-04-29 Ivy Bridge-EX[20] Ivy Bridge-EP[20] Gladden Ivy Bridge Ivy Bridge-E[21] Ivy Bridge Ivy Bridge-M
Tock Haswell Haswell 4 3 HSW, CRW (Crystal Well)
with Iris Pro[22][23]
HSX 2013-06-02 Haswell-EX Haswell-EP Haswell-DT Haswell-E Haswell-DT[24] Haswell-MB (notebooks)
Haswell-LP (ultrabooks)[24]
Refresh Haswell Refresh,
Devil's Canyon[25]
4 HSW, CRW (Crystal Well)
with Iris Pro[22][23]
—} 2014-05-11,
2014-06-02
No server version released Devil's Canyon No mobile version
released
Tick (Process) 14 nm[19] Broadwell[26] 5 4 BDW BDX 2014-09-05 Broadwell-EX[27] Broadwell-EP[27] Broadwell-DE Broadwell-DT Broadwell-E Broadwell-DT Broadwell-H
Broadwell-U
Broadwell-Y
Tock (Architecture) Skylake[26] Skylake[26] 6 5 SKL SKX 2015-08-05[28] Skylake-SP Skylake-DE Skylake-DT/H Skylake-X Skylake Skylake-H
Skylake-U
Skylake-Y
Optimization
(Refresh)
[4][29][30][31]
Kaby Lake[32] 7 6 KBL 2017-01-03[33] Only 1P server (Xeon E3) version released Kaby Lake-DT/H
cores: 4 (4/8)
Kaby Lake-X[34] Kaby Lake Kaby Lake-H
Kaby Lake-U
Kaby Lake-Y
Kaby Lake R[35][36] 8 KBL-R 2017-08-21[36] Only mobile version released Kaby Lake R
Coffee Lake 8, 9[37] E-2xxx CFL 2017-10-05[38] Cascade Lake-SP
Cooper Lake (Q2'20)
Cascade Lake-AP Coffee Lake-DT/H
cores: 6 (12)
Skylake-X Refresh Coffee Lake-S
Coffee Lake-R
Coffee Lake-H
Coffee Lake-U
Coffee Lake-H Refresh
Whiskey Lake,
Amber Lake[39]
8 WHL
AML
2018-08-28[39] Only mobile version released Whiskey Lake-U
Amber Lake-Y
Comet Lake[40] 10 CML 2019-08-21[40] No server version released Comet Lake-W Comet Lake-S Comet Lake-H
Comet Lake-U
Architecture Cypress Cove[41] Rocket Lake[41] 11 RKL 2021-03-30[42] Rocket Lake-S
Process 10 nm Palm Cove Cannon Lake 8 CNL 2018-05-16[43] Only mobile version released Cannon Lake-U
Architecture Sunny Cove Ice Lake[44] 10 3 ICL 2019-08-01[45] Ice Lake-SP (1H21)[46] Ice Lake-U
Ice Lake-Y
Optimization[31] Willow Cove Tiger Lake[31] 11 TGL 2020-09-02[47] Only mobile version released Tiger Lake-H35
Tiger Lake-UP3
Tiger Lake-UP4
Architecture Intel 7 Golden Cove Alder Lake 12 ADL 2021-11-04 No server / WS version released Alder Lake-S Alder Lake-H
Alder Lake-P
Alder Lake-U
Sapphire Rapids[48] 4 SPR 2022 Sapphire Rapids-SP TBA Only server / WS version released
Optimization TBA Raptor Lake 13 RPL 2022 No server / WS version released TBA
Emerald Rapids 5 EMR 2023 Emerald Rapids-SP TBA Only server / WS version released
Tick Intel 4[49] Meteor Lake[50] 14 MTL 2023 No server / WS version released TBA
Tick Intel 3 Granite Rapids[51] 6 GNR 2024 Granite Rapids-SP TBA Only server / WS version released
Tick Intel 20A Arrow Lake[52] 15 ARL 2024 No server / WS version released TBA
Tick Intel 18A Lunar Lake 16 LNL TBA No server / WS version released TBA
Change
(step)
Fabri­cation
process
Micro-
architecture
Code names
for step
Intel
Generation
Desktop
Intel
Generation
Xeon
Intel Microcode
shortcut(s)
Desktop/WS[7][8]
Intel Microcode
shortcut(s)
Xeon/Server
Release
date
8P/4P Server 4P/2P Server/WS Embedded Xeon 1P Xeon Enthusiast/WS Desktop Mobile
Processors

Atom roadmap[edit]

With Silvermont Intel tried to start Tick-Tock in Atom architecture but problems with the 10 nm process did not allow to do this. In the table below instead of Tick-Tock steps Process-Architecture-Optimization are used. There is no official confirmation that Intel uses Process-Architecture-Optimization for Atom but it allows us to understand what changes happened in each generation.

Atom roadmap[53]
Change Fabri­cation
process
Micro-
architecture

(Abbr.)[13]
Code names
for step
Release
date
Processors/SoCs
MID, Smartphone Tablet Netbook Nettop Embedded Server CE
Process / Architecture 45 nm Bonnell (BNL) Bonnell 2008 Silverthorne Diamondville
Optimization Bonnell 2010 Lincroft Pineview Tunnel Creek
Stellarton
Sodaville
Groveland
Process 32 nm Saltwell 2011 Medfield (Penwell & Lexington) & Clover Trail+ (Cloverview) Clover Trail (Cloverview) Cedar Trail (Cedarview) Centerton & Briarwood Berryville
Process / Architecture 22 nm Silvermont (SLM) Silvermont 2013 Merrifield (Tangier)[54] & Moorefield (Anniedale)[55] & Slayton Bay Trail-T
(Valleyview)
Bay Trail-M
(Valleyview)
Bay Trail-D
(Valleyview)
Bay Trail-I
(Valleyview)
Avoton
Rangeley
Un­known
Process 14 nm[53] Airmont 2014 Binghamton & Riverton Cherry Trail-T (Cherryview)[56] Braswell[57] Denverton
Cancelled
Un­known
Architecture Goldmont[58]
(GLM)
Goldmont 2016 Broxton Cancelled Broxton Cancelled
Apollo Lake
Apollo Lake Apollo Lake Un­known Denverton Un­known
Architecture Goldmont Plus
(GLM+, GLP)
Goldmont Plus 2017 Un­known Gemini Lake Gemini Lake Gemini Lake Un­known Un­known Un­known
Optimization Goldmont Plus 2019 Un­known Gemini Lake Refresh Gemini Lake Refresh Gemini Lake Refresh Un­known Un­known Un­known
Process / Architecture 10 nm Tremont Tremont 2020 Un­known Jasper Lake Jasper Lake Jasper Lake Elkhart Lake Snow Ridge Un­known
Architecture Intel 7 Gracemont Gracemont 2021 Un­known Un­known Alder Lake (hybrid) Un­known Un­known
Process / Architecture Intel 3 Un­known Un­known Un­known Un­known Un­known Un­known Un­known Un­known Sierra Forest-AP Un­known

Note: There is further the Xeon Phi. It has up to now undergone four development steps with a current top model that got the code name Knights Landing (shortcut: KNL;[13] the predecessor code names all had the leading term Knights in their name) that is derived from the Silvermont architecture as used for the Intel Atom series but realized in a shrunk 14 nm (FinFET) technology.[59] In 2018, Intel announced that Knights Landing and all further Xeon Phi CPU models were discontinued.[60] However, Intel's Sierra Forest and subsequent Atom-based Xeon CPUs are likely a spiritual successor to Xeon Phi.

Both[edit]

See also[edit]

References[edit]

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  2. ^ "Intel tick–tock model". intel.com. Intel Corporation. Retrieved 2014-11-02. A yearly product cadence moves the industry forward in a predictable fashion that can be planned in advance.
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  8. ^ a b Linux* Processor Microcode Data File Version 20180312 on 3/12/2018
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  13. ^ a b c d "X86 / Amd64 library". GitHub. 25 October 2021.
  14. ^ "Intel Launches Fastest Processor on the Planet". Intel.com (Press release). Intel Corporation. November 17, 2008.
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  35. ^ Products formerly Kaby Lake R
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  59. ^ Intel veröffentlicht Xeon Phi mit bis zu 7 Teraflops
  60. ^ "Product Change Notification 116378 - 00" (PDF). Intel.com. Retrieved 25 July 2018.

External links[edit]