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TopoR (Topological Router) is an EDA program developed and maintained by Eremex company, based in Russia. It is dedicated to laying out a printed circuit board (PCB). It currently lacks schematic capture and library editing (which have to be done using third-party software), but features a powerful autorouter and a set of tools intended to reduce the amount of effort needed for manual routing of a PCB. The most recognizable feature of TopoR is absence of preferred routing directions, which results in unusual looking PCBs.


Printed circuit board sample

Work on a flexible topological router began in 1988, when it became clear that the traditional methods of routing with regular and irregular grids (grid-based routers and shape-based routers) and consecutive wiring with locked-down geometry were a dead-end solution.

1996 saw the release of the first version of a topological router that actually came to be used by industrial enterprises. The FreeStyle Router ran under MS-DOS and successfully routed dual-layer boards. This early router showed the advantages of an innovative approach to routing and high efficiency of the models, algorithms, and software implementation. A 1.44MB floppy disk was enough for the program and accompanying examples.

The first Windows version of the topological router was released in 2001 and named TopoR. The program routed not only dual-layer but also multilayer printed circuit boards.

General information[edit]

Wires consisting of lines only
Wires consisting of lines and arcs

Routing of the wiring topology is done automatically and flexibly; angles are not limited to 90° and 45°.

Efficient use of PCB space and absence of preferred routing directions in layers considerably reduces electromagnetic crosstalks.

TopoR routes all connections, even if this entails violating design constraints. Such violations can be automatically corrected later.

When you move objects (such as components and vias) around, wire length and shape are optimized automatically with appropriate clearance.

The user is free to choose from two ways to calculate the wire shape: with or without arcs. The first method involves wires consisting of lines only. The other makes wires keep appropriate clearance when circling pads and consist of arcs and lines.

TopoR simultaneously optimizes several alternative variants of the layout. Variants with the worst parameters (total wire length and number of vias) will be removed.

TopoR has an automatic component placement feature. The procedure can be used both for all components of the board and only for components in a specific area. It is not comparable to the quality of the manual placement, but it can be used as a preparation step for manual placement.

The minimum and desired clearances for each net can be specified.

Reduced wire width

TopoR automatically reduces the width of a wire that approaches a narrow pad (or one with a diameter that is less than the width of the wire), or when it passes through bottlenecks (for example, between the pads of a component).

Wire-to-pad transitions use teardrop-style smoothing. The use of this procedure at the design stage helps avoid violations in design-rule checking when teardrops are added in the CAM editor.

BGA component routing

TopoR can recognize BGA (Ball Grid Array) component areas and apply a special strategy for routing them. This helps reduce the number of vias, the density of connections, and in some cases the number of routing layers.

In Russian (language of the developers), topor means "axe".

Single-layer printed circuit board sample

See also[edit]



External links[edit]