Instead of the instruction set architecture being implemented in hardware, or translated by specialized hardware, the Crusoe runs a software abstraction layer, or a virtual machine, known as the Code Morphing Software (CMS). The CMS translates machine code instructions received from programs into native instructions for the microprocessor. In this way, the Crusoe can emulate other instruction set architectures (ISAs). This is used to allow the microprocessors to emulate the Intel x86 instruction set.
OS and software limitations as of 2022
The Crusoe processor supports MMX but not SSE. As of 2022, most browsers on Windows and Linux, and some other programs, need SSE or SSE2 support; therefore, that software will no longer run on the Crusoe platform. For example, Firefox dropped support for systems without SSE2 long ago, although K-Meleon could run without SSE on Windows XP. The Efficeon processor added support for SSE and SSE2.
The Crusoe was notable for its method of achieving x86 compatibility. Instead of the instruction set architecture being implemented in hardware, or translated by specialized hardware, the Crusoe runs a software abstraction layer, or a virtual machine, known as the Code Morphing Software (CMS). The CMS translates machine code instructions received from programs into native instructions for the microprocessor. In this way, the Crusoe can emulate other instruction set architectures (ISAs). This is used to allow the microprocessors to emulate the Intel x86 instruction set. In theory, it is possible for the CMS to be modified to emulate other ISAs. Transmeta demonstrated Crusoe executing Java bytecode by translating the bytecodes into instructions in its native instruction set. The addition of an abstraction layer between the x86 instruction stream and the hardware means that the hardware architecture can change without breaking compatibility, just by modifying the CMS. For example, Transmeta Efficeon — a second-generation Transmeta design — has a 256-bit-wide VLIW core versus the 128-bit core of the Crusoe. Efficeon also supports SSE instructions.
The Crusoe is a VLIW microprocessor that executes bundles of instructions, termed molecules by Transmeta. Each molecule contains multiple instructions, termed atoms. The Code Morphing Software translates x86 instructions into native instructions. The native instructions are 32 bits long. Instructions that meet a set of conditions can be executed simultaneously and are combined to form a 64- or 128-bit molecule containing two or four atoms, respectively. In the event that there are not enough instructions to fill a molecule, the software inserts NOPs as padding to fill out empty slots. This is required in all VLIW architectures and is criticised for being inefficient, which is why there are molecules of two separate lengths.
The Crusoe performs in software some of the functionality traditionally implemented in hardware (e.g. instruction re-ordering), resulting in simpler hardware with fewer transistors. The relative simplicity of the hardware means that Crusoe consumes less power (and therefore generates less heat) than other x86-compatible microprocessors running at the same frequency. A 700 MHz Crusoe ran x86 programs at the speed of a 500 MHz Pentium III x86 processor, although the Crusoe processor was smaller and cheaper than the corresponding Intel processor.
The Crusoe was available in two cores: the TM3200 for embedded applications and the TM5400 for low-power personal computing. Both were based on the same architecture but differed in clock frequency and peripheral support. The TM3200 operated at clock frequencies of 333–400 MHz. It has a 64 KB instruction cache, a 32 KB data cache and no L2 cache. The TM3200 has an integrated memory controller supports only SDRAM and a PCI interface. It measures 77 mm² and uses a 1.5 V power supply, dissipating less than 1.5 W of power (typically). The TM5400 operated at clock frequencies of 500–800 MHz. Unlike the TM3200, the TM5400 has LongRun power reduction technology. It has a 64 KB instruction cache, a 64 KB data cache and a 256 KB unified L2 cache. The integrated memory controller supports both SDRAM and DDR SDRAM. It also has a PCI interface. It measures 73 mm² and uses a 1.10 V 1.6f V power supply, dissipating 0.5–1.5 W typically and a maximum of 6 W.
Transmeta was a fabless semiconductor company, without the facilities to fabricate their designs. Instead, both processors were fabricated by IBM Microelectronics, the semiconductor business of International Business Machines (IBM). IBM fabricated the Crusoe in a 0.18 µm CMOS process with five levels of copper interconnect.
- Blue Coat Systems Proxy SG210-25 (800Mhz TM5800)
- Casio Cassiopeia Fiva MPC-205/206E
- Casio MPC-701 Pen Tablet PC
- Compaq TC1000
- Compaq T5300, T5500, T5510, T5515, T5700 and T5710 Thin Clients
- Dialogue Flybook A33i/V33i
- ECS EZ-Tablet EZ30
- ECS i-Buddie A907
- Fujitsu FMV-BIBLO LOOX s5/53w, t5/53w, t5/53
- Fujitsu / Siemens Futro S300 (800Mhz TM5800)
- Fujitsu LifeBook P1032, P1100, P1120, P2040, P2110, P2120
- Gateway Touch Pad
- HP Compaq t5300 Thin Client (with TM5600 533 MHz)
- HP Compaq t5500 Thin Client (with TM5800 733 MHz)
- HP Compaq t5700 Thin Client (with TM5800 733 MHz or 1 GHz)
- NEC LaVie MX
- MSI PenNote3100 (TM5800 at 1GHz)
- NEC PowerMate Eco
- NEC Versa DayLite/UltraLite
- OQO Model 01 and 01+
- Orion Multisystems DT-12 desktop Cluster Workstation
- Orion Multisystems DS-96 deskside Cluster Workstation
- PCChips A530 Series Notebook
- RLX ServerBlade 1000t
- Sharp Actius/Mebius MM10
- SONICblue ProGear information appliance
- Sony VAIO PCG-U1 and PCG-U3
- Sony VAIO PCG-C1VE, PCG-C1VP, PCG-C1VPK and PCG-C1VN
- Syntax A530 laptop (TM5600 clocked at 599.174 MHz)
- TDV Vison V800XPT Tablet
- Toshiba Libretto L1, L2, L3, L3 Adidas Edition and L5 (L1–L3 at 600 MHz and L5 at 800 MHz)
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Although the FPU/multimedia unit can handle the same data types as Intel’s MMX instructions, Crusoe chips don’t have the new 128-bit registers defined by Intel’s SSE (Streaming SIMD Extensions). Transmeta says Crusoe could emulate SSE-type instructions and registers, but there’s not enough software support for SSE to justify the effort at this time.
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