A multigate device or multiple-gate field-effect transistor (MuGFET) refers to a MOSFET (metal–oxide–semiconductor field-effect transistor) that incorporates more than one gate into a single device. The multiple gates may be controlled by a single gate electrode, wherein the multiple gate surfaces act electrically as a single gate, or by independent gate electrodes. A multigate device employing independent gate electrodes is sometimes called a multiple-independent-gate field-effect transistor (MIGFET).
Multigate transistors are one of the several strategies being developed by CMOS semiconductor manufacturers to create ever-smaller microprocessors and memory cells, colloquially referred to as extending Moore's law.
Development efforts into multigate transistors have been reported by AMD, Hitachi, IBM, Infineon Technologies, Intel Corporation, TSMC, Freescale Semiconductor, University of California, Berkeley, and others, and the ITRS predicted correctly that such devices will be the cornerstone of sub-32 nm technologies. The primary roadblock to widespread implementation is manufacturability, as both planar and non-planar designs present significant challenges, especially with respect to lithography and patterning. Other complementary strategies for device scaling include channel strain engineering, silicon-on-insulator-based technologies, and high-κ/metal gate materials.
Dual-gate MOSFETs are commonly used in very high frequency (VHF) mixers and in sensitive VHF front-end amplifiers. They are available from manufacturers such as Motorola, NXP Semiconductors, and Hitachi.
Dozens of multigate transistor variants may be found in the literature. In general, these variants may be differentiated and classified in terms of architecture (planar vs. non-planar design) and the number of channels/gates (2, 3, or 4).
Planar double-gate transistor
The first international demonstration of the multigate devices family using thin Silicon film was performed with a double-gate MOSFET. The double-gate control of silicon-on-insulator (SOI) transistors was used to force the whole silicon film (interface layers and volume) in strong inversion (called “Volume-Inversion MOSFET”) or strong accumulation (called “Volume-Accumulation MOSFET”). This original method of transistor operation, at the origin of the unique electrostatic properties and scalability of multigate devices, offered excellent device performance, in particular, great increases in subthreshold slope, transconductance, and drain current. A simulation program and experiments on SIMOX structures was used to study this new type of device.
Planar double-gate transistors employ conventional planar (layer by layer) manufacturing processes to create double-gate devices, avoiding more stringent lithography requirements associated with non-planar, vertical transistor structures. In planar double-gate transistors the drain–source channel is sandwiched between two independently fabricated gate/gate-oxide stacks. The primary challenge in fabricating such structures is achieving satisfactory self-alignment between the upper and lower gates.
FlexFET is a planar, independently double-gated transistor with a damascene metal top gate MOSFET and an implanted JFET bottom gate that are self-aligned in a gate trench. This device is highly scalable due to its sub-lithographic channel length; non-implanted ultra-shallow source and drain extensions; non-epi raised source and drain regions; and gate-last flow. FlexFET is a true double-gate transistor in that (1) both the top and bottom gates provide transistor operation, and (2) the operation of the gates is coupled such that the top gate operation affects the bottom gate operation and vice versa. Flexfet was developed and is manufactured by American Semiconductor, Inc.
FinFET (fin field-effect transistor) is a type of non-planar transistor, or "3D" transistor. The first finfet transistor type was known under the name of fully DEpleted Lean-channel TrAnsistor, or DELTA transistor. It was developed by Digh Hisamoto and his team of researchers at Hitachi Central Research Laboratory in 1989, and introduced in 1991, when it was published in a paper by Hitachi Central Research Laboratory researchers Digh Hisamoto, T. Kaga and E. Takeda.
Based on the earlier DELTA transistor design, the term FinFET (fin field-effect transistor) was coined in a December 2000 paper by Digh Hisamoto from Hitachi Central Research Laboratory with UC Berkeley researchers including Chenming Hu, Tsu-Jae King-Liu, Jeffrey Bokor, and Wen-Chin Lee, to describe a non-planar, double-gate transistor built on an SOI substrate. The FinFET is a variation on traditional MOSFETs distinguished by the presence of a thin silicon "fin" inversion channel on top of the substrate, allowing the gate to make two points of contact: the left and right sides of the fin. The thickness of the fin (measured in the direction from source to drain) determines the effective channel length of the device. The wrap-around gate structure provides a better electrical control over the channel and thus helps in reducing the leakage current and overcoming other short-channel effects.
In current usage the term FinFET has a less precise definition. Among microprocessor manufacturers, AMD, IBM, and Freescale describe their double-gate development efforts as FinFET development, whereas Intel avoids using the term when describing their closely related tri-gate architecture. In the technical literature, FinFET is used somewhat generically to describe any fin-based, multigate transistor architecture regardless of number of gates.
A 25 nm transistor operating on just 0.7 volt was demonstrated in December 2002 by TSMC (Taiwan Semiconductor Manufacturing Company). The "Omega FinFET" design is named after the similarity between the Greek letter omega (Ω) and the shape in which the gate wraps around the source/drain structure. It has a gate delay of just 0.39 picosecond (ps) for the N-type transistor and 0.88 ps for the P-type.
FinFET can also have two electrically independent gates, which gives circuit designers more flexibility to design with efficient, low-power gates.
In 2012, Intel started using FinFETs for its future commercial devices. Leaks suggest that Intel's FinFET has an unusual shape of a triangle rather than rectangle, and it is speculated that this might be either because a triangle has a higher structural strength and can be more reliably manufactured or because a triangular prism has a higher area-to-volume ratio than a rectangular prism, thus increasing switching performance.
In September 2012, GlobalFoundries announced plans to offer a 14-nanometer process technology featuring FinFET three-dimensional transistors in 2014. The next month, the rival company TSMC announced start early or "risk" production of 16 nm FinFETS in November 2013.
- 16 nm FinFET (Q4 2014),
- 16 nm FinFET+ ( [clarify] Q4 2014),
- 16 nm FinFET "Turbo" (estimated in 2015–2016).
AMD released GPUs using their Polaris chip architecture and made on 14 nm FinFET in June 2016 . The company has tried to produce a design to provide a "generational jump in power efficiency" while also offering stable frame rates for graphics, gaming, virtual reality, and multimedia applications.
Tri-gate (3D) transistor
This section needs to be updated.December 2016)(
Tri-gate or 3D transistor (not to be confused with 3D microchips) fabrication is used by Intel Corporation for the nonplanar transistor architecture used in Ivy Bridge, Haswell and Skylake processors. These transistors employ a single gate stacked on top of two vertical gates (a single gate wrapped over 3 sides of the channel), allowing essentially three times the surface area for electrons to travel. Intel reports that their tri-gate transistors reduce leakage and consume far less power than current transistors. This allows up to 37% higher speed or a power consumption at under 50% of the previous type of transistors used by Intel.
Intel explains: "The additional control enables as much transistor current flowing as possible when the transistor is in the 'on' state (for performance), and as close to zero as possible when it is in the 'off' state (to minimize power), and enables the transistor to switch very quickly between the two states (again, for performance)." Intel has stated that all products after Sandy Bridge will be based upon this design.
Intel was the first company to announce this technology. In September 2002, Intel announced their creation of "triple-gate transistors" to maximize "transistor switching performance and decreases power-wasting leakage". A year later, in September 2003, AMD announced that it was working on similar technology at the International Conference on Solid State Devices and Materials. No further announcements of this technology were made until Intel's announcement in May 2011, although it was stated at IDF 2011, that they demonstrated a working SRAM chip based on this technology at IDF 2009.
On April 23, 2012, Intel released a new line of CPUs, termed Ivy Bridge, which feature tri-gate transistors. Intel has been working on its tri-gate architecture since 2002, but it took until 2011 to work out mass-production issues. The new style of transistor was described on May 4, 2011, in San Francisco. Intel factories are expected to make upgrades over 2011 and 2012 to be able to manufacture the Ivy Bridge CPUs. As well as being used in Intel's Ivy Bridge chips for desktop PCs, the new transistors will also be used in Intel's Atom chips for low-powered devices.
The term tri-gate is sometimes used generically to denote any multigate FET with three effective gates or channels.
Gate-all-around (GAA) FET
Gate-all-around FETs are similar in concept to FinFETs except that the gate material surrounds the channel region on all sides. Depending on design, gate-all-around FETs can have two or four effective gates. Gate-all-around FETs have been successfully characterized both theoretically and experimentally. They have also been successfully etched onto InGaAs nanowires, which have a higher electron mobility than silicon.
Multi-bridge channel (MBC) FET
Planar transistors have been the core of integrated circuits for several decades, during which the size of the individual transistors has steadily decreased. As the size decreases, planar transistors increasingly suffer from the undesirable short-channel effect, especially "off-state" leakage current, which increases the idle power required by the device.
In a multigate device, the channel is surrounded by several gates on multiple surfaces. Thus it provides better electrical control over the channel, allowing more effective suppression of "off-state" leakage current. Multiple gates also allow enhanced current in the "on" state, also known as drive current. Multigate transistors also provide a better analog performance due to a higher intrinsic gain and lower channel length modulation. These advantages translate to lower power consumption and enhanced device performance. Nonplanar devices are also more compact than conventional planar transistors, enabling higher transistor density which translates to smaller overall microelectronics.
The primary challenges to integrating nonplanar multigate devices into conventional semiconductor manufacturing processes include:
- Fabrication of a thin silicon "fin" tens of nanometers wide
- Fabrication of matched gates on multiple sides of the fin
BSIMCMG106.0.0, officially released on March 1, 2012 by UC Berkeley BSIM Group, is the first standard model for FinFETs. BSIM-CMG is implemented in Verilog-A. Physical surface-potential-based formulations are derived for both intrinsic and extrinsic models with finite body doping. The surface potentials at the source and drain ends are solved analytically with poly-depletion and quantum mechanical effects. The effect of finite body doping is captured through a perturbation approach. The analytic surface potential solution agrees closely with the 2-D device simulation results. If the channel doping concentration is low enough to be neglected, computational efficiency can be further improved by a setting a specific flag (COREMOD = 1).
All of the important multi-gate (MG) transistor behavior is captured by this model. Volume inversion is included in the solution of Poisson’s equation, hence the subsequent I–V formulation automatically captures the volume-inversion effect. Analysis of electrostatic potential in the body of MG MOSFETs provided a model equation for short-channel effects (SCE). The extra electrostatic control from the end gates (top/bottom gates) (triple or quadruple-gate) is also captured in the short-channel model.
- Three-dimensional integrated circuit
- Semiconductor device
- Clock gating
- High-κ dielectric
- Next-generation lithography
- Extreme ultraviolet lithography
- Immersion lithography
- Strain engineering
- Very-large-scale integration (VLSI)
- Neuromorphic engineering
- Bit slicing
- 3D printing
- Silicon on insulator (SOI)
- Floating-gate MOSFET
- High electron mobility transistor
- Field-effect transistor
- Tetrode transistor
- Pentode transistor
- Quantum circuit
- Quantum gate
- Transistor model
- Die shrink
- Risch, L. "Pushing CMOS Beyond the Roadmap", Proceedings of ESSCIRC, 2005, p. 63.
- Table39b Archived September 27, 2007, at the Wayback Machine
- "3N201 (Motorola) - Dual Gate Mosfet Vhf Amplifier". Doc.chipfind.ru. Retrieved 2014-03-10.
- "3SK45 datasheet pdf datenblatt - Hitachi Semiconductor - SILICON N-CHANNEL DUAL GATE MOSFET". Alldatasheet.com. Retrieved 2014-03-10.
- "BF1217WR" (PDF). Retrieved 2015-05-10.
- F. BALESTRA, S. CRISTOLOVEANU, M. BENACHIR, J.BRINI, T. ELEWA, Double-gate Silicon-On-Insulator transistor with volume inversion: A new device with greatly enhanced performance, IEEE Electron Device Letters EDL-8, pp. 410–412, Sept. 1987
- Wong, H-S.; Chan, K.; Taur, Y. (December 10, 1997). Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel. Electron Devices Meeting, 1997. IEDM '97. Technical Digest. pp. 427–430. doi:10.1109/IEDM.1997.650416. ISBN 978-0-7803-4100-5. ISSN 0163-1918.
- Wilson, D.; Hayhurst, R.; Oblea, A.; Parke, S.; Hackler, D. "Flexfet: Independently-Double-Gated SOI Transistor With Variable Vt and 0.5V Operation Achieving Near Ideal Subthreshold Slope" SOI Conference, 2007 IEEE International Archived April 3, 2015, at the Wayback Machine
- "What is Finfet?". Computer Hope. April 26, 2017. Retrieved 4 July 2019.
- "IEEE Andrew S. Grove Award Recipients". IEEE Andrew S. Grove Award. Institute of Electrical and Electronics Engineers. Retrieved 4 July 2019.
- "The Breakthrough Advantage for FPGAs with Tri-Gate Technology" (PDF). Intel. 2014. Retrieved 4 July 2019.
- Hisamoto, D.; Kaga, T.; Takeda, E. (June 1991). "Impact of the vertical SOI 'DELTA' structure on planar device technology" (PDF). IEEE Transactions on Electron Devices. 38 (6): 1419–1424. doi:10.1109/16.81634. Archived from the original (PDF) on 2016-12-01.
- Hisamoto, D. et al. (1991) "Impact of the vertical SOI 'Delta' Structure on Planar Device Technology" IEEE Trans. Electron. Dev. 41 p. 745.
- Hisamoto, Digh; Hu, Chenming; Bokor, J.; King, Tsu-Jae; Anderson, E.; et al. (December 2000). "FinFET-a self-aligned double-gate MOSFET scalable to 20 nm". IEEE Transactions on Electron Devices. 47 (12): 2320–2325. CiteSeerX 10.1.1.211.204. doi:10.1109/16.887014.
- Hisamoto, Digh; Hu, Chenming; Huang, Xuejue; Lee, Wen-Chin; Kuo, C.; et al. (May 2001). "Sub-50 nm P-channel FinFET" (PDF). IEEE Transactions on Electron Devices. 48 (5): 880–886. doi:10.1109/16.918235.
- "AMD Newsroom". Amd.com. 2002-09-10. Archived from the original on 2010-05-13. Retrieved 2015-07-07.
- "Intel Silicon Technology Innovations". Intel.com. Archived from the original on September 3, 2011. Retrieved 2014-03-10.
- Rostami, M.; Mohanram, K. (2011). "IEEE Xplore Abstract - Dual- Independent-Gate FinFETs for Low Power Logic Circuits". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30 (3): 337–349. doi:10.1109/TCAD.2010.2097310.
- "Intel's FinFETs are less fin and more triangle". EE Times. Retrieved 2014-03-10.
- "Globalfoundries looks leapfrog fab rivals with new process". EE Times. Retrieved 2014-03-10.
- "TSMC taps ARM's V8 on road to 16 nm FinFET". EE Times. Retrieved 2014-03-10.
- Josephine Lien, Taipei; Steve Shen, [Monday 31 March 2014]. "TSMC likely to launch 16 nm FinFET+ process at year-end 2014, and "FinFET Turbo" later in 2015-16". DIGITIMES. Retrieved 2014-03-31.CS1 maint: Uses authors parameter (link)
- Smith, Ryan. "The AMD Radeon RX 480 Preview: Polaris Makes Its Mainstream Mark". Retrieved 2018-06-03.
- "AMD Demonstrates Revolutionary 14nm FinFET Polaris GPU Architecture". AMD. Retrieved 2016-01-04.
- "High-performance, high-bandwidth IP platform for Samsung 14LPP process technology". 2017-03-22.
- "Samsung and eSilicon Taped Out 14nm Network Processor with Rambus 28G SerDes Solution". 2017-03-22.
- Cartwright J. (2011). "Intel enters the third dimension". Nature. doi:10.1038/news.2011.274. Retrieved 2015-05-10.
- Intel to Present on 22-nm Tri-gate Technology at VLSI Symposium (ElectroIQ 2012) Archived April 15, 2012, at the Wayback Machine
- "Below 22nm, spacers get unconventional: Interview with ASM". ELECTROIQ. Retrieved 2011-05-04.
- High Performance Non-Planar Tri-gate Transistor Architecture; Dr. Gerald Marcyk. Intel, 2002
- [dead link]
- "AMD Details Its Triple-Gate Transistors". Xbitlabs.com. Archived from the original on 2014-03-10. Retrieved 2014-03-10.
- "IDF 2011: Intel Looks to Take a Bite Out of ARM, AMD With 3D FinFET Tech". DailyTech. Archived from the original on 2014-03-10. Retrieved 2014-03-10.
- Miller, Michael J. "Intel Releases Ivy Bridge: First Processor with "Tri-Gate" Transistor". PC Magazine.
- "Intel Reinvents Transistors Using New 3-D Structure". Intel. Retrieved 5 April 2011.
- "Transistors go 3D as Intel re-invents the microchip". Ars Technica. 5 May 2011. Retrieved 7 May 2011.
- Murray, Matthew (4 May 2011). "Intel's New Tri-Gate Ivy Bridge Transistors: 9 Things You Need to Know". PC Magazine. Retrieved 7 May 2011.
- Singh N, et al. (2006). "High-Performance fully depleted Silicon Nanowire Gate-All-Around CMOS devices". IEEE Electron Device Letters. 27 (5): 383–386. Bibcode:2006IEDL...27..383S. doi:10.1109/LED.2006.873381.
- Dastjerdy, E.; Ghayour, R.; Sarvari, H. (August 2012). "Simulation and analysis of the frequency performance of a new silicon nanowire MOSFET structure". Physica E. 45: 66–71. Bibcode:2012PhyE...45...66D. doi:10.1016/j.physe.2012.07.007.
- "First Experimental Demonstration of Gate-all-around III-V MOSFETs by Top-down Approach" (PDF). Retrieved 2015-05-10.
- Cutress, Ian. "Samsung Announces 3nm GAA MBCFET PDK, Version 0.1". www.anandtech.com.
- Subramanian V (2010). "Multiple gate field-effect transistors for future CMOS technologies". IETE Technical Review. 27 (6): 446–454. doi:10.4103/0256-4602.72582. Archived from the original on March 23, 2012.
- Subramanian (5 Dec 2005). "Device and circuit-level analog performance trade-offs: a comparative study of planar bulk FETs versus FinFETs". Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International: 898–901.
- "BSIMCMG Model". UC Berkeley. Archived from the original on 2012-07-21.