Universal Verification Methodology
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The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM (e Reuse Methodology) for the e Verification Language developed by Verisity Design in 2001. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor Graphics, and Synopsys.
In December 2009, a technical subcommittee of Accellera — a standards organization in the electronic design automation (EDA) industry — voted to establish the UVM and decided to base this new standard on the Open Verification Methodology (OVM-2.1.1), a verification methodology developed jointly in 2007 by Cadence Design Systems and Mentor Graphics.
On February 21, 2011, Accellera approved the 1.0 version of UVM. UVM 1.0 includes a Reference Guide, a Reference Implementation in the form of a SystemVerilog base class library, and a User Guide.
The sequencer is responsible for three main functions:
- Put the DUV (Design Under Verification) and the verification environment into an initialization state
- Configuring the verification environment and DUV
- The entire DUV scenario generation
In this stage the DUT (Device Under Test) and the environment it is in should be set to the conditions desired before the simulation. Likely, this includes:
- Loading memory, with any type of needed initial conditions
- Pin settings on the DUT, such as power and high impedance
- Register settings that can not be altered during simulation such as mode bits or if part of the environment reg
- Verification component settings that can not be altered during simulation
- Agent - A container that emulates and verifies DUT devices
- Blocking - An interface that blocks tasks from other interfaces until it completes
- DUT - Device under test, what you are actually testing
- DUV - Device Under Verification
- Component - A portion of verification intellectual property that has interfaces and functions.
- Transactor - see component
- Verification Environment Configuration - those settings in the DUT and environment that are alterable while the simulation is running
- VIP - verification intellectual property
UVM allows the use of Macros
|name||function||related to||parameters||purpose||Type of Macro|
|'uvm_create||object constructor||`uvm_send||Sequence or Item||to create the object and allow user to set values via overloading or parameter passing||Sequence action macro|
|`uvm_send||processor||`uvm_create||Sequence or Item||processes what is created by `uvm_create without randomization||Sequence Action Macros for Pre-Existing Sequences|
|`uvm_do||processor||`uvm_create||Sequence or Item||executes class or item with randomization||Sequence action macro|