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V-by-One HS is an electrical digital signaling standard that can run at faster speeds over inexpensive twisted-pair copper cables than Low-voltage differential signaling, or LVDS. It was originally developed by THine Electronics, Inc. in 2007 for high-definition televisions but since 2010 V-by-One HS has been widely adopted in various markets such as document processing, automotive infotainment systems, industrial cameras and machine vision, robotics and amusement equipments.
While high-definition televisions had generally used LVDS to transmit pixel data, timing-skew problems among conductors appeared by increasing data rate based on requirements of higher-resolution and more color-depth. V-by-One HS, by its SerDes and CDR(Clock recovery) technology, achieves the high speed of 3.75 Gbit/s for each pair of conductors, decreasing the number of conductors, therefore reducing the total costs including cables and connectors. This solves skew problems and reduces electromagnetic interference (or EMI) and power consumption.
Outline of V-by-One HS
Historically flat panel televisions used LVDS as its internal interface to transmit pixel data but, in accordance with televisions’ higher resolution and expansion in color depth, televisions had to face problems such as increasing numbers of twisted-pair cables and tangible skews problems among cables. V-by-One HS is a standard of a high-speed SerDes, introducing CDR specification and equalizer, that achieves 3.75 Gbit/s (giga bits per second), solves skew problems, and reduces the power consumption and EMI. On behalf of such features, V-by-One HS enables to reduce total costs of interface systems, including costs of cables and connectors. V-by-One HS standard is an open standard and its specification has been delivered by THine Electronics.
Equalizer and CDR technology
Equalizer of V-by-One HS improves data transmitting quality compared with LVDS interface. Because of this specification, it enables to expand data transmission between longer distances.
In addition, clock data recovery or CDR solves the skew problems that were more tangible in LVDS interface than ever. CDR technology eliminates any clock cables that LVDS requires with particular fixed frequency clock, resulted in lowering EMI noises. V-by-One HS supports wide range speed from 600 Mbit/s up to 3.75 Gbit/s, enabling lower energy consumption than interface with fixed rate.
LVDS adopters can switch smoothly from LVDS to V-by-One HS without significant changes in products designed.
Development of V-by-One HS Technology
V-by-One HS has been originally developed to replace internal interfaces of digital pixel displays.
LCDs, different from cathode ray tube (CRT) displays, have to use digital signaling to show each pixel. While notebook PCs started replacing CRT displays to LCDs, pixel data were transmitted as parallel data, interface systems found the problem that more than 20 cables were required to transmit data with 18 bits color depth for each 6-bit RGB color as well as lack of space for cables and difficulty of adjusting skews.
In order to solve these problems FPD-Link which uses low-voltage differential signaling, or LVDS, were adopted into LCDs. LVDS, defined by the ANSI/TIA/EIA-644-A standard, is a differential signaling system that can run at high speed. LVDS works in serial data transmission. As the main applications had 18 bits color depth in early adoption of FPD-Link, a 7-bit wide differential cable pair for each of 3 channels with another channel for clock became used. By this adoption of FPD-Link, internal interface systems of LCDs could reduce the 22 pair cables into 8 pairs with high-speed serial transmission. The Video Electronics Standards Association (VESA) adopted this as a video standard specification and FPD-Link has penetrated wider as LCD interface.
However, in accordance with the fact that LCDs required much higher definition and more color depth as well as more frame rate, FPD-Link faced problems that input pixel data for LCDs increased exponentially and the number of LVDS cables soared as well. For example, full HD television (1920 x 1080 pixels) with a 10-bit color depth and double frame rate requires 24 FPD-Link differential pairs. Such a case has to adjust skews at the level of several hundreds of picoseconds because of much higher-speed clock and data rate. In addition, since LVDS requires a fixed clock frequency that concentrates spectrums, the interface systems have to minimize electromagnetic interference.
Furthermore, since FPD-Link mainly uses electrical digital signaling between zero volts (the ground level) and 1.2 volts based on its standard, it became a significant constraint of designing higher density LSIs. Under such circumstances, many substitutable interfaces such as DVI, HDMI, DisplayPort, and V-by-One HS are offered and adopted widely.
DVI and HDMI have widely penetrated as external interfaces between equipments since DVI and HDMI can adjust skews. HDMI also requires hardware implementation of HDCP, a content protection scheme. On the other hand, they had not been adopted as internal interfaces to replace FPD-Link because they require license fees, have functions that are not needed for internal data transmission, and their high voltage differential signals make chip design and manufacturing more difficult. DisplayPort, standardized by VESA to replace FPD-Link, is expecting to penetrate widely. DisplayPort has a similar specification of bias to PCI Express and is expected to have small barriers to design. However, DisplayPort has additional complexity because it is designed to allow one source device to drive multiple monitors, so it uses standardized link speeds and packetized data transfer. This requires DisplayPort sink devices to have circuitry needed to discard packets targeted at other sink devices and to extract data from packets targeted at themselves, and have a memory buffer in order to deal with the speed mismatch between the standardized link speed and the speed the display requires. Multiple monitors might need data at the same time as each other, but DisplayPort can only transmit one micro-packet to one monitor on one differential pair at a time. This is solved by having some micro-packets sent earlier to the monitors before they are needed and having their data buffered at the target monitors until each monitor's display controller needs the data.
Under such circumstances, V-by-One HS has been developed. The largest differences by V-by-One HS from the other interfaces can be seen in its equalizer and clock/data recovery (CDR) technology. V-by-One HS uses an equalizer in the receiver to help the receiver clean up an incoming signal and therefore helps boost signal integrity. This boost in signal integrity allows V-by-One HS achieve a speed of 3.75 Gbit/s which is higher than what FPD-Link permits. In addition, Its CDR technology solves the skew problems in FPD-Link and eliminates the need for a separate clock signal that generates more electromagnetic interference.
Because of its higher-speed data transmitting ability, V-by-One HS is expected to reduce the numbers of cables, connectors, their related spaces within the equipments and finally the total costs. For example, Ultra definition panel (UD panel, 3840 x 2160 pixels) requires only 16-pair cables with V-by-One HS technology while it needs 96 pairs of general LVDS cables. V-by-One HS supports wide range of transmitting speeds. Engineers of set makers can adopt it smoothly without significant changes from the existing LVDS interface.
- Flat panel displays, including tablets and televisions
- Document processing and multi-functional printers
- Automotive infotainment systems
- Industrial cameras and machine vision
- Amusement equipments
The V-by-One HS Standard is open and delivered by THine Electronics. As of June 30, 2012, the most updated version is “V-by-One HS Standard Version 1.4.”
- FPD-Link - often mistakenly called LVDS. It is the standard V-by-One HS is trying to replace.
- DisplayPort - Internal DisplayPort (iDP) is an adaptation of DisplayPort for internal use in flat screen televisions. It is a contemporary competitor to V-by-One HS that is promoted by the Video Electronics Standards Association. It removes all DRM, the auxiliary data channel, allows the designer to use more lanes than regular DisplayPort to deal with higher bandwidth needs, and requires one signaling speed, 3.24 GHz, instead of a clock speed that is tied to the incoming pixel rate. This interface allows the designer to use one to an unlimited number of lanes unlike regular DisplayPort which is restricted to 4 lanes maximum. Each iDP lane runs at 3.24 GHz. Due to 8b/10b overhead which enables clock recovery without a separate clock signal lane, each lane carries 2.592 gigabits per second after the overhead is removed. Padding is used to deal with the difference between the throughput supplied by iDP and the raw video throughput.
- THine Electronics - The designer and maintainer of V-by-One HS.