4.200 / 12 March 2021
|Operating system||Linux, FreeBSD, Microsoft Windows (via Cygwin)|
|License||Perl Artistic License and GNU Lesser General Public License|
Verilator is a free and open-source software tool which converts Verilog (a hardware description language) to a cycle-accurate behavioral model in C++ or SystemC. It is restricted to modeling the synthesizable subset of Verilog and the generated models are cycle-accurate, 2-state, with synthesis (zero delay) semantics. As a consequence, the models typically offer higher performance than the more widely used event-driven simulators, which can process the entire Verilog language and model behavior within the clock cycle. Verilator is now used within academic research, open source projects and for commercial semiconductor development. It is part of the growing body of free EDA software.
Verilator has seen its widest adoption in the academic and open source communities. The semiconductor industry has been more cautious in its adoption of an open source tool, and has the financial means to use commercial alternatives.
Researchers have used Verilator to develop new co-simulation environments, as part of general ASIC and FPGA design flows and in performance and power analysis. Verilator is also a popular tool for student dissertations, for example.
Verilator is an open source tool, and has in turn been adopted by a number of other projects. The Fedora Electronic Lab  has adopted Verilator as part of its open source design flow for Fedora 11. The OpenRISC architecture from OpenCores includes a cycle accurate reference model, generated from Verilog using Verilator. A recent paper described how the regression test suite for GCC could be run against a Verilator model of the OpenRISC 1200 as a way of detecting errors in the Verilog RTL implementation. TestDrive Profiling Master  tool provides the virtual FPGA environment using Verilator.
Commercially, Philips Semiconductors (now NXP) have led the way. Their use of Verilator is becoming more widespread, for example within application notes. More recently Art of Silicon have described their use of Verilator on a farm of Linux processors as a route to faster regression testing of their commercial designs. The current maintainer of Verilator identified 27 companies and universities who had reported use of Verilator or contributed to its development, including Intel, Arm, CSR, Broadcom, Raytheon, Infineon, Stanford University, Imperial College London and Embecosm.
Verilator's user manual provides a short history. The tool originated in 1994 with a team led by Paul Wasson at the Core Logic Group at Digital Equipment Corporation (DEC). It was used to convert Verilog code to C for co-simulation with a C based CPU model of the Alpha processor. During the mid-1990s Duane Galbi took over responsibility for development and the technology was adopted by other groups in DEC. In 1998 DEC released the source code.
Since 2001 the technology has been developed by Wilson Snyder and others as part of the Veripool open source project. A SystemC mode was added and the tool rewritten from scratch in C++, leading to an increase in performance.
Technology and key features
Verilator converts synthesizable Verilog to C++ or SystemC. It can handle all versions of Verilog and also some SystemVerilog and Sugar/PSL assertions. The approach is closer to synthesis than event driven simulation. The entire design is flattened (that is, all modules are expanded to create one module). Static analysis is used to eliminate wires and schedule all processes at model generation time. Since this is a cycle-accurate model, all intra-cycle delays are ignored. A C++ class is generated with a function which takes 2-state values on input ports and advance them to values on output ports at the next clock edge.
SystemC is supported by providing a wrapper class using SystemC ports, and with sensitivity to the clock(s), which will drive the ports of the underlying C++ model.
Verilator supports automatically partitioning designs into multiple threads, also potentially improving performance.
This section needs expansion. You can help by adding to it. (March 2009)
Using with MATLAB
Verilator converts synthesizable Verilog to C++, while C++ library could be compiled into a MEX file using MATLAB interface to C++. This is how Verilog designs can be directly simulated from MATLAB. Using compiled C++ models with MATLAB is faster than using co-simulation interfaces with a separate HDL simulator. There is an open-source project called vmodel that compiles Verilog into a MEX file using Verilator, and provides a set of functions for model simulation from MATLAB.
- W Snyder, "Verilator and SystemPerl". North American SystemC Users' Group, Design Automation Conference, June 2004.
- "Release 4.200". 12 March 2021. Retrieved 20 March 2021.
- Oyama Masashiro, Tanaka Daisuke and Shimizu Naohiki. "C-language based Hardware and Software Co-Simulation Environment Featuring sfl2vl and Verilator", Joho Shori Gakkai Shinpojiumu Ronbunshu (Information Processing Society of Japan Symposium Thesis Collection), 2004 (10), 34–40.
- P Garcia and K Compton. "A Reconfigurable Hardware Interface for a Modern Computing System". FCCM 2007 (15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines), 23–25 April 2007, 73–84, (the DOI listed for this paper, doi:10.1109/FCCM.2007.49 is incorrect)
- Eric S. Chung, James C. Hoe, Babak Falsafi. "PROTO FLEX: Co-Simulation for Component-wise FPGA Emulator Development", WARFP 2006 (2nd Workshop on Architecture Research using FPGA Platforms), Austin Texas, 12 February 2006.
- Chin-Chie Huang, Jaw-Wei Chi, Tzu-Ching Lin, Lin-Wei Tsao, Yi-Jung Chen and Chia-Lin Yang. "System-Level Performance/Power Evaluation Framework for Platform-based SOC", Department of Computer Science and Information Engineering, National Taiwan University, 2008.
- Siddhartha Devalapalli. "Development of SystemC Modules from HDL for System-on-Chip Applications", MSc Dissertation, University of Tennessee, Knoxville, August 2004.
- Jeremy Bennett, Embecosm, "Processor verification using open source tools and the GCC regression test suite: A case study", Design Verification Club meeting, Bristol, Cambridge & Eindhoven, 20 September 2010, 
- Jean-Paul van Itegem, Philips Semiconductors (now NXP), quoted in Deep Chip 25 October 2005 
- Chuck Peplinski, "Hardware Prefetch and Data Cache Optimization Tools for Nexperia Media Processors", NXP Semiconductors, 11 January 2007 "Archived copy" (PDF). Archived from the original (PDF) on 20 August 2008. Retrieved 13 March 2009. CS1 maint: discouraged parameter (link) CS1 maint: archived copy as title (link)
- Rich Porter, "Designer Productivity - An Alternate Approach", National Microelectronics Institute, System-Level Design Network meeting, Engineers House, Bristol, UK 24 September 2009, available at www.slideshare.net/richporter/20090924aosnmiesl
- Rich Porter, "Architecture for Massively Parallel HDL Simulations", Design Verification Club meeting, Bristol, Cambridge & Eindhoven, 20 September 2010, "Archived copy" (PDF). Archived from the original (PDF) on 13 March 2012. Retrieved 24 September 2010. CS1 maint: discouraged parameter (link) CS1 maint: archived copy as title (link)
- Wilson Snyder, Cavium Networks, "Verilator: Fast, Free, But for Me?", Design Verification Club meeting, Bristol, Cambridge & Eindhoven, 20 September 2010, 
- Wilson Snyder, "Verilator-3.700", 7 January 2009