x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU.
In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-assisted virtualization capabilities while attaining reasonable performance. In 2005 and 2006, both Intel (VT-x) and AMD (AMD-V) introduced limited hardware virtualization support that allowed simpler virtualization software but offered very few speed benefits. Greater hardware support, which allowed substantial speed improvements, came with later processor models.
The following discussion focuses only on virtualization of the x86 architecture protected mode.
In protected mode the operating system kernel runs at a higher privilege such as ring 0, and applications at a lower privilege such as ring 3. In software-based virtualization, a host OS has direct access to hardware while the guest OSs have limited access to hardware, just like any other application of the host OS. One approach used in x86 software-based virtualization to overcome this limitation is called ring deprivileging, which involves running the guest OS at a ring higher (lesser privileged) than 0.
Three techniques made virtualization of protected mode possible:
- Binary translation is used to rewrite in terms of ring 3 instructions certain ring 0 instructions, such as POPF, that would otherwise fail silently or behave differently when executed above ring 0,:3 making the classic trap-and-emulate virtualization impossible.:1 To improve performance, the translated basic blocks need to be cached in a coherent way that detects code patching (used in VxDs for instance), the reuse of pages by the guest OS, or even self-modifying code.
- A number of key data structures used by a processor need to be shadowed. Because most operating systems use paged virtual memory, and granting the guest OS direct access to the MMU would mean loss of control by the virtualization manager, some of the work of the x86 MMU needs to be duplicated in software for the guest OS using a technique known as shadow page tables.:5:2 This involves denying the guest OS any access to the actual page table entries by trapping access attempts and emulating them instead in software. The x86 architecture uses hidden state to store segment descriptors in the processor, so once the segment descriptors have been loaded into the processor, the memory from which they have been loaded may be overwritten and there is no way to get the descriptors back from the processor. Shadow descriptor tables must therefore be used to track changes made to the descriptor tables by the guest OS.
- I/O device emulation: Unsupported devices on the guest OS must be emulated by a device emulator that runs in the host OS.
These techniques incur some performance overhead due to lack of MMU virtualization support, as compared to a VM running on a natively virtualizable architecture such as the IBM System/370.:10:17 and 21
On traditional mainframes, the classic type 1 hypervisor was self-standing and did not depend on any operating system or run any user applications itself. In contrast, the first x86 virtualization products were aimed at workstation computers, and ran a guest OS inside a host OS by embedding the hypervisor in a kernel module that ran under the host OS (type 2 hypervisor).
There has been some controversy whether the x86 architecture with no hardware assistance is virtualizable as described by Popek and Goldberg. VMware researchers pointed out in a 2006 ASPLOS paper that the above techniques made the x86 platform virtualizable in the sense of meeting the three criteria of Popek and Goldberg, albeit not by the classic trap-and-emulate technique.:2–3
A different route was taken by other systems like Denali, L4, and Xen, known as paravirtualization, which involves porting operating systems to run on the resulting virtual machine, which does not implement the parts of the actual x86 instruction set that are hard to virtualize. The paravirtualized I/O has significant performance benefits as demonstrated in the original SOSP'03 Xen paper.
The initial version of x86-64 (AMD64) did not allow for a software-only full virtualization due to the lack of segmentation support in long mode, which made the protection of the hypervisor's memory impossible, in particular, the protection of the trap handler that runs in the guest kernel address space.:11 and 20 Revision D and later 64-bit AMD processors (as a rule of thumb, those manufactured in 90 nm or less) added basic support for segmentation in long mode, making it possible to run 64-bit guests in 64-bit hosts via binary translation. Intel did not add segmentation support to its x86-64 implementation (Intel 64), making 64-bit software-only virtualization impossible on Intel CPUs, but Intel VT-x support makes 64-bit hardware assisted virtualization possible on the Intel platform.:4
On some platforms, it is possible to run a 64-bit guest on a 32-bit host OS if the underlying processor is 64-bit and supports the necessary virtualization extensions.
In 2005 and 2006, Intel and AMD (working independently) created new processor extensions to the x86 architecture. The first generation of x86 hardware virtualization addressed the issue of privileged instructions. The issue of low performance of virtualized system memory was addressed with MMU virtualization that was added to the chipset later.
Central processing unit
Virtual 8086 mode
Based on painful experiences with the 80286 protected mode, which by itself was not suitable enough to run concurrent DOS applications well, Intel introduced the virtual 8086 mode in their 80386 chip, which offered virtualized 8086 processors on the 386 and later chips. Hardware support for virtualizing the protected mode itself, however, became available 20 years later.
AMD virtualization (AMD-V)
AMD developed its first generation virtualization extensions under the code name "Pacifica", and initially published them as AMD Secure Virtual Machine (SVM), but later marketed them under the trademark AMD Virtualization, abbreviated AMD-V.
AMD-V capability also features on the Athlon 64 and Athlon 64 X2 family of processors with revisions "F" or "G" on socket AM2, Turion 64 X2, and Opteron 2nd generation and third-generation, Phenom and Phenom II processors. The APU Fusion processors support AMD-V. AMD-V is not supported by any Socket 939 processors. The only Sempron processors which support it are APUs and Huron, Regor, Sargas desktop CPUs.
AMD Opteron CPUs beginning with the Family 0x10 Barcelona line, and Phenom II CPUs, support a second generation hardware virtualization technology called Rapid Virtualization Indexing (formerly known as Nested Page Tables during its development), later adopted by Intel as Extended Page Tables (EPT).
As of 2019, all modern Zen-based AMD processors support AMD-V.
The CPU flag for AMD-V is "svm". This may be checked in BSD derivatives via dmesg or sysctl and in Linux via
/proc/cpuinfo. Instructions in AMD-V include VMRUN, VMLOAD, VMSAVE, CLGI, VMMCALL, INVLPGA, SKINIT, and STGI.
Intel virtualization (VT-x)
Previously codenamed "Vanderpool", VT-x represents Intel's technology for virtualization on the x86 platform. On November 13, 2005, Intel released two models of Pentium 4 (Model 662 and 672) as the first Intel processors to support VT-x. The CPU flag for VT-x capability is "vmx"; in Linux, this can be checked via
/proc/cpuinfo, or in macOS via
"VMX" stands for Virtual Machine Extensions, which adds 13 new instructions: VMPTRLD, VMPTRST, VMCLEAR, VMREAD, VMWRITE, VMCALL, VMLAUNCH, VMRESUME, VMXOFF, VMXON, INVEPT, INVVPID, and VMFUNC. These instructions permit entering and exiting a virtual execution mode where the guest OS perceives itself as running with full privilege (ring 0), but the host OS remains protected.
As of 2015[update], almost all newer server, desktop and mobile Intel processors support VT-x, with some of the Intel Atom processors as the primary exception. With some motherboards, users must enable Intel's VT-x feature in the BIOS setup before applications can make use of it.
Intel started to include Extended Page Tables (EPT), a technology for page-table virtualization, since the Nehalem architecture, released in 2008. In 2010, Westmere added support for launching the logical processor directly in real mode – a feature called "unrestricted guest", which requires EPT to work.
Since the Haswell microarchitecture (announced in 2013), Intel started to include VMCS shadowing as a technology that accelerates nested virtualization of VMMs. The virtual machine control structure (VMCS) is a data structure in memory that exists exactly once per VM, while it is managed by the VMM. With every change of the execution context between different VMs, the VMCS is restored for the current VM, defining the state of the VM's virtual processor. As soon as more than one VMM or nested VMMs are used, a problem appears in a way similar to what required shadow page table management to be invented, as described above. In such cases, VMCS needs to be shadowed multiple times (in case of nesting) and partially implemented in software in case there is no hardware support by the processor. To make shadow VMCS handling more efficient, Intel implemented hardware support for VMCS shadowing.
VIA virtualization (VIA VT)
VIA Nano 3000 Series Processors and higher support VIA VT virtualization technology compatible with Intel VT-x. EPT is present in Zhaoxin ZX-C, a descendent of VIA QuadCore-E & Eden X4 similar to Nano C4350AL.
Interrupt virtualization (AMD AVIC and Intel APICv)
In 2012, AMD announced their Advanced Virtual Interrupt Controller (AVIC) targeting interrupt overhead reduction in virtualization environments. This technology, as announced, does not support x2APIC. In 2016, AVIC is available on the AMD family 15h models 6Xh (Carrizo) processors and newer.
Also in 2012, Intel announced a similar technology for interrupt and APIC virtualization, which did not have a brand name at its announcement time. Later, it was branded as APIC virtualization (APICv) and it became commercially available in the Ivy Bridge EP series of Intel CPUs, which is sold as Xeon E5-26xx v2 (launched in late 2013) and as Xeon E5-46xx v2 (launched in early 2014).
Graphics processing unit
Graphics virtualization is not part of the x86 architecture. Intel Graphics Virtualization Technology (GVT) provides graphics virtualization as part of more recent Gen graphics architectures. Although AMD APUs implement the x86-64 instruction set, they implement AMD's own graphics architectures (TeraScale, GCN and RDNA) which do not support graphics virtualization. Larrabee was the only graphics microarchitecture based on x86, but it likely did not include support for graphics virtualization.
I/O MMU virtualization (AMD-Vi and Intel VT-d)
An input/output memory management unit (IOMMU) allows guest virtual machines to directly use peripheral devices, such as Ethernet, accelerated graphics cards, and hard-drive controllers, through DMA and interrupt remapping. This is sometimes called PCI passthrough.
An IOMMU also allows operating systems to eliminate bounce buffers needed to allow themselves to communicate with peripheral devices whose memory address spaces are smaller than the operating system's memory address space, by using memory address translation. At the same time, an IOMMU also allows operating systems and hypervisors to prevent buggy or malicious hardware from compromising memory security.
Both AMD and Intel have released their IOMMU specifications:
- AMD's I/O Virtualization Technology, "AMD-Vi", originally called "IOMMU"
- Intel's "Virtualization Technology for Directed I/O" (VT-d), included in most high-end (but not all) Nehalem and newer Intel processors
In addition to the CPU support, both motherboard chipset and system firmware (BIOS or UEFI) need to fully support the IOMMU I/O virtualization functionality for it to be usable. Only the PCI or PCI Express devices supporting function level reset (FLR) can be virtualized this way, as it is required for reassigning various device functions between virtual machines. If a device to be assigned does not support Message Signaled Interrupts (MSI), it must not share interrupt lines with other devices for the assignment to be possible. All conventional PCI devices routed behind a PCI/PCI-X-to-PCI Express bridge can be assigned to a guest virtual machine only all at once; PCI Express devices have no such restriction.
Network virtualization (VT-c)
- Intel's "Virtualization Technology for Connectivity" (VT-c).
PCI-SIG Single Root I/O Virtualization (SR-IOV)
- Address translation services (ATS) supports native IOV across PCI Express via address translation. It requires support for new transactions to configure such translations.
- Single-root IOV (SR-IOV or SRIOV) supports native IOV in existing single-root complex PCI Express topologies. It requires support for new device capabilities to configure multiple virtualized configuration spaces.
- Multi-root IOV (MR-IOV) supports native IOV in new topologies (for example, blade servers) by building on SR-IOV to provide multiple root complexes which share a common PCI Express hierarchy.
In SR-IOV, the most common of these, a host VMM configures supported devices to create and allocate virtual "shadows" of their configuration spaces so that virtual machine guests can directly configure and access such "shadow" device resources. With SR-IOV enabled, virtualized network interfaces are directly accessible to the guests, avoiding involvement of the VMM and resulting in high overall performance; for example, SR-IOV achieves over 95% of the bare metal network bandwidth in NASA's virtualized datacenter and in the Amazon Public Cloud.
- Comparison of application virtual machines
- Comparison of platform virtualization software
- Hardware-assisted virtualization
- I/O virtualization
- Network virtualization
- Operating system-level virtualization
- Timeline of virtualization development
- Virtual machine
- List of IOMMU-supporting hardware
- Second Level Address Translation (SLAT)
- Message Signaled Interrupts (MSI)
- A Comparison of Software and Hardware Techniques for x86 Virtualization, Keith Adams and Ole Agesen, VMware, ASPLOS’06 October 21–25, 2006, San Jose, California, USA Archived 2010-08-20 at the Wayback Machine"Surprisingly, we find that the first-generation hardware support rarely offers performance advantages over existing software techniques. We ascribe this situation to high VMM/guest transition costs and a rigid programming model that leaves little room for software flexibility in managing either the frequency or cost of these transitions.
- "Intel Virtualization Technology Processor Virtualization Extensions and Intel Trusted execution Technology" (PDF). Intel.com. 2007. Archived (PDF) from the original on 2015-05-21. Retrieved 2016-12-12.
- "USENIX Technical Program - Abstract - Security Symposium - 2000". Usenix.org. 2002-01-29. Archived from the original on 2010-06-10. Retrieved 2010-05-02.
- "A Comparison of Software and Hardware Techniques for x86 Virtualization" (PDF). VMware. Archived (PDF) from the original on 20 August 2010. Retrieved 8 September 2010.
- U.S. Patent 6,397,242
- U.S. Patent 6,704,925
- "Virtualization: architectural considerations and other evaluation criteria" (PDF). VMware. Archived (PDF) from the original on 6 February 2011. Retrieved 8 September 2010.
- U.S. Patent 6,496,847
- "VMware and Hardware Assist Technology" (PDF). Archived (PDF) from the original on 2011-07-17. Retrieved 2010-09-08.
- "Xen and the Art of Virtualization" (PDF). Archived (PDF) from the original on 2014-09-29.
- "How retiring segmentation in AMD64 long mode broke VMware". Pagetable.com. 2006-11-09. Archived from the original on 2011-07-18. Retrieved 2010-05-02.
- "VMware and CPU Virtualization Technology" (PDF). VMware. Archived (PDF) from the original on 2011-07-17. Retrieved 2010-09-08.
- "VMware KB: Hardware and firmware requirements for 64bit guest operating systems". Kb.vmware.com. Archived from the original on 2010-04-19. Retrieved 2010-05-02.
- "Software and Hardware Techniques for x86 Virtualization" (PDF). Archived from the original (PDF) on 2010-01-05. Retrieved 2010-05-02.
- Yager, Tom (2004-11-05). "Sending software to do hardware's job | Hardware - InfoWorld". Images.infoworld.com. Archived from the original on 2014-10-18. Retrieved 2014-01-08.
- "33047_SecureVirtualMachineManual_3-0.book" (PDF). Archived (PDF) from the original on 2012-03-05. Retrieved 2010-05-02.
- "What are the main differences between Second-Generation AMD Opteron processors and first-generation AMD Opteron processors?". amd.com. Archived from the original on April 15, 2009. Retrieved 2012-02-04.
- "What virtualization enhancements do Quad-Core AMD Opteron processors feature?". amd.com. Archived from the original on April 16, 2009. Retrieved 2012-02-04.
- To see if your processor supports hardware virtualization Archived 2012-11-25 at the Wayback Machine Intel 2012.
- INTEL (October 2019). "Intel® 64 and IA-32 Architectures Software Developer's Manual". intel.com. Intel Corporation. Retrieved 2020-01-04.
- "Intel Virtualization Technology List". Ark.intel.com. Archived from the original on 2010-10-27. Retrieved 2010-05-02.
- "Windows Virtual PC: Configure BIOS". Microsoft. Archived from the original on 2010-09-06. Retrieved 2010-09-08.
- Neiger, Gil; A. Santoni; F. Leung; D. Rodgers; R. Uhlig. "Intel Virtualization Technology: Hardware Support for Efficient Processor Virtualization" (PDF). Intel Technology Journal. Intel. 10 (3): 167–178. doi:10.1535/itj.1003.01. Archived from the original (PDF) on 2012-09-25. Retrieved 2008-07-06.
- Gillespie, Matt (2007-11-12). "Best Practices for Paravirtualization Enhancements from Intel Virtualization Technology: EPT and VT-d". Intel Software Network. Intel. Archived from the original on 2008-12-26. Retrieved 2008-07-06.
- "First the Tick, Now the Tock: Next Generation Intel Microarchitecture (Nehalem)" (PDF) (Press release). Intel. Archived (PDF) from the original on 2009-01-26. Retrieved 2008-07-06.
- "Technology Brief: Intel Microarchitecture Nehalem Virtualization Technology" (PDF). Intel. 2009-03-25. Archived (PDF) from the original on 2011-06-07. Retrieved 2009-11-03.
- http://2013.asiabsdcon.org/papers/abc2013-P5A-paper.pdf:[permanent dead link] "Intel added unrestricted guest mode on Westmere micro-architecture and later Intel CPUs, it uses EPT to translate guest physical address access to host physical address. With this mode, VMEnter without enable paging is allowed."
- http://download.intel.com/products/processor/manual/326019.pdf:[permanent dead link] "If the “unrestricted guest” VM-execution control is 1, the “enable EPT” VM-execution control must also be 1"
- "4th-Gen Intel Core vPro Processors with Intel VMCS Shadowing" (PDF). Intel. 2013. Retrieved 2014-12-16.
- Understanding Intel Virtualization Technology (VT). Archived September 8, 2014, at the Wayback Machine Retrieved 2014-09-01
- The 'what, where and why' of VMCS shadowing. Archived 2014-09-03 at the Wayback Machine Retrieved 2014-09-01
- VIA Introduces New VIA Nano 3000 Series Processors Archived January 22, 2013, at the Wayback Machine
- "Notebook Solution: Kaixian ZX-C Processor + VX11PH Chipset" (PDF).
- Wei Huang, Introduction of AMD Advanced Virtual Interrupt Controller Archived 2014-07-14 at the Wayback Machine, XenSummit 2012
- Jörg Rödel (August 2012). "Next-generation Interrupt Virtualization for KVM" (PDF). AMD. Archived (PDF) from the original on 2016-03-04. Retrieved 2014-07-12.
- "[Xen-devel] [RFC PATCH 0/9] Introduce AMD SVM AVIC". www.mail-archive.com. Archived from the original on 2 February 2017. Retrieved 4 May 2018.
- Jun Nakajimaa (2012-12-13). "Reviewing Unused and New Features for Interrupt/APIC Virtualization" (PDF). Intel. Archived (PDF) from the original on 2015-04-21. Retrieved 2014-07-12.
- Khang Nguyen (2013-12-17). "APIC Virtualization Performance Testing and Iozone". software.intel.com. Archived from the original on 2014-07-14. Retrieved 2014-07-12.
- "Product Brief Intel Xeon Processor E5-4600 v2 Product Family" (PDF). Intel. 2014-03-14. Archived (PDF) from the original on 2014-07-14. Retrieved 2014-07-12.
- "Intel platform hardware support for I/O virtualization". Intel.com. 2006-08-10. Archived from the original on 2007-01-20. Retrieved 2012-02-04.
- "Linux virtualization and PCI passthrough". IBM. Archived from the original on 1 November 2009. Retrieved 10 November 2010.
- "AMD I/O Virtualization Technology (IOMMU) Specification Revision 1.26" (PDF). Archived (PDF) from the original on 2011-01-24. Retrieved 2011-05-24.
- "Intel Virtualization Technology for Directed I/O (VT-d) Architecture Specification". Archived from the original on 2013-04-03. Retrieved 2012-02-04.
- "Intel Virtualization Technology for Directed I/O (VT-d) Supported CPU List". Ark.intel.com. Archived from the original on 2010-10-27. Retrieved 2012-02-04.
- "PCI-SIG Engineering Change Notice: Function Level Reset (FLR)" (PDF). pcisig.com. 2006-06-27. Archived (PDF) from the original on 2016-03-04. Retrieved 2014-01-10.
- "Xen VT-d". xen.org. 2013-06-06. Archived from the original on 2014-02-09. Retrieved 2014-01-10.
- "How to assign devices with VT-d in KVM". linux-kvm.org. 2014-04-23. Archived from the original on 2015-03-10. Retrieved 2015-03-05.
- "Intel Virtualization Technology for Connectivity (VT-c)" (PDF). Intel.com. Archived (PDF) from the original on 2016-02-22. Retrieved 2018-02-14.
- "PCI-SIG I/O Virtualization (IOV) Specifications". Pcisig.com. 2011-03-31. Archived from the original on 2012-01-15. Retrieved 2012-02-04.
- "Intel Look Inside: Intel Ethernet" (PDF). Intel. November 27, 2014. p. 104. Archived (PDF) from the original on March 4, 2016. Retrieved March 26, 2015.
- Yaozu Dong, Zhao Yu, Greg Rose (2008). "SR-IOV Networking in Xen: Architecture, Design and Implementation". usenix.org. USENIX. Archived from the original on 2014-01-09. Retrieved 2014-01-10.CS1 maint: uses authors parameter (link)
- Patrick Kutch; Brian Johnson; Greg Rose (September 2011). "An Introduction to Intel Flexible Port Partitioning Using SR-IOV Technology" (PDF). Intel. Archived (PDF) from the original on August 7, 2015. Retrieved September 24, 2015.
- "NASA's Flexible Cloud Fabric: Moving Cluster Applications to the Cloud" (PDF). Intel. Archived (PDF) from the original on 2012-12-22. Retrieved 2014-01-08.
- "Enhanced Networking in the AWS Cloud". Scalable Logic. 2013-12-31. Archived from the original on 2014-01-09. Retrieved 2014-01-08.
- "Enhanced Networking in the AWS Cloud - Part 2". Scalable Logic. 2013-12-31. Archived from the original on 2014-01-10. Retrieved 2014-01-08.