This article does not cite any sources. (July 2009) (Learn how and when to remove this template message)
WARFT or WAran Research FoundaTion is a nonprofit organization promoting interdisciplinary research among undergraduate students in the city of Chennai, India. Professor N. Venkateswaran founded the group in 2000 and continues to manage it as of 2011. The aim of WARFT is to understand and model the brain to enable drug discovery so that spastic children can live a normal life.
Since its inception, WARFT has researched brain modeling, supercomputing and associated areas. The goal of WARFT is to unravel the connectivity of the human brain regions through the MMINi-DASS project. Biologically accurate brain simulations require massive computational power and thus another research initiative at WARFT is the MIP Project directed towards evolving a design method for the development of a tera-operations supercomputing cluster.
Undergraduate research trainees at WARFT engage themselves in the areas of neuroscience, supercomputing architectures, processor design towards deep sub-micrometre, power-aware computing, low power issues, mixed signal design, fault tolerance and testing, digital signal processing. WARFT conducts Dhi Yantra, a workshop on brain modeling and supercomputing every year.
WARFT's mission is twofold. Firstly to promote innovation and research awareness in the minds of young undergraduate students. In this respect, WARFT conducts a two-year part-time Research Awareness Programme and Training (RAPT) for undergraduate students. Secondly to solve the mysteries of the brain and to hasten the discovery of drugs that can cure brain diseases.
Undergraduate research initiatives
There are two main inter-disciplinary research initiatives at WARFT :
The Multi Million Neuron interconnectivity - Dendrite Axon Soma and Synapse
The MMINi-DASS project is a large-scale brain simulation carried out to predict interconnectivity of a specific brain region and makes use of fMRI BOLD response of brain regions. This results in understanding of brain dynamics from the most fundamental level to cognitive and behavioral aspects. Modeling individual brain entities is a challenging task. Predicting their interconnectivity through simulation requires enormous computing power and thus, the project banks on the exponentially increasing computing power and its decreasing cost.
The Memory In Processor SuperComputer On Chip (MIP SCOC) and the Silicon Operating System (SILICOS)
The immense computational demand imposed by the MMINi-DASS PROJECT has given rise to the novel supercomputer design known as the MIP SCOC. The MIP approach incorporates the memory within the logic, reminiscent of The Berkeley IRAM Project. In the MIP SCOC architecture, memory is physically and logically integrated with the functional units of the processor. This bit-level integration of processing logic and memory has led to a tremendous increase in functionality of a single MIP SCOC node.
The MIP SCOC architecture includes powerful ALFU (Algorithm Level Functional units) like chain matrix adders, multipliers, sorters, multiple operand adders and graph theoretic units like Depth-First-Search, Breadth-First-Search. This introduces a higher level of abstraction through the algorithm-level instructions (ALISA). A single ALISA is equivalent to multiple parallel VLIW. The MIP SCOC architecture includes an on-chip compiler (Compiler-On-Silicon) to generate the required instructions to feed the ALFUs of the MIP node. The Primary COS (PCOS) partitions the incoming problem according to the algorithms involved. Each SCOS generates the instructions corresponding to that column. A distributed control design is employed specific to ALFU population type (forming different heterogeneous cores) enabling parallel operation of a very large number of ALFUs.
WARFT is divided into seven research groups:
- CHARAKA: the Neurosciences Group
- VISHWAKARMA: the Computer Architecture Group
- MARCONI: the Mixed Signal Group
- BHASKARA: Power Aware Design for Nanotech DSP Architectures Group
- NAREN: Testing and Fault Tolerant Group
- RAMANUJAN: Nanotech Design Methodologies Group
- HARDY: Low Power Architectures for Matrix Algorithm Group
Dhi Yantra is a workshop on brain modeling and supercomputing organized by WARFT every year. Three editions of this workshop, featuring scientists and researchers from various fields and geography, have been held. The fourth workshop was held in Chennai, India on July 10, 11 and 12, 2009.