Wafer-level packaging

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Texas Instruments TWL6032 in a wafer-level package

Wafer-level packaging (WLP) is the technology of packaging an integrated circuit while still part of the wafer, in contrast to the more conventional method of slicing the wafer into individual circuits (dice) and then packaging them. WLP is essentially a true chip-scale package (CSP) technology, since the resulting package is practically of the same size as the die. Wafer-level packaging allows integration of wafer fab, packaging, test, and burn-in at wafer level in order to streamline the manufacturing process undergone by a device from silicon start to customer shipment.

Wafer-level packaging consists of extending the wafer fab processes to include device interconnection and device protection processes. Most other kinds of packaging do wafer dicing first, and then put the individual die in a plastic package and attach the solder bumps. Wafer-level packaging involves attaching the top and bottom outer layers of packaging and the solder bumps to integrated circuits while still in the wafer, and then dicing the wafer.

There is no single industry-standard method of wafer-level packaging at present.

A major application area of WLPs are smartphones due to the size constraints. For example, the Apple iPhone 5 has at least eleven different WLPs, the Samsung Galaxy S3 has six WLPs and the HTC One X has seven. Functions provided WLPs in smartphones include sensors, power management, wireless, etc.[1] In fact, it has recently been rumored that the iPhone 7 will use fan-out wafer-level packaging technology in order to achieve a thinner and lighter model.[2][3][needs update]

Wafer-level chip scale packaging (WL-CSP) is the smallest package currently available on the market and is produced by OSAT (Outsourced Semiconductor Assembly and Test) companies, such as Advanced Semiconductor Engineering (ASE).[4] A WL-CSP or WLCSP package is just a bare Die with a redistribution layer (interposer or I/O pitch) to rearrange the pins or contacts on the die so that they can be big enough and have sufficient spacing so that they can be handled just like a BGA package.[5]

There are two kinds of wafer level packaging: Fan-in and Fan-Out. Fan-in WLCSP packages have an interposer that is the same size as that of the Die, where as Fan-Out WLCSP packages have an interposer that is larger than the Die, similar to conventional BGA packages, the difference being that the interposer is built directly atop the die, instead of the die being attached to it and reflowed using the flip chip method. This is also true in fan-in WLSCP packages. [6][7] In both cases, the die with its interposer may be covered in encapsulating material such as epoxy.

In February 2015, it was discovered that a WL-CSP chip in the Raspberry Pi 2 had issues with xenon flashes (or any other bright flashes of longwave light), inducing the photoelectric effect within the chip.[8] Thus, careful consideration concerning exposure to extremely bright light will need to be given with wafer-level packaging.

See also[edit]


  1. ^ Korczynski, Ed (May 5, 2014). "Wafer-level packaging of ICs for mobile systems of the future". Semiconductor Manufacturing & Design Community. Archived from the original on August 16, 2018. Retrieved September 24, 2018.
  2. ^ By Aaron Mamiit, Tech Times. “Apple Wants a Slimmer iPhone 7 and Will Reportedly Use Fan-Out Packaging Technology.” April 1, 2016. Retrieved April 8, 2016.
  3. ^ By Yoni Heisler, BGR. “Report details new tech Apple is using to make the iPhone 7 thinner and lighter.” March 31, 2016. Retrieved April 14, 2016.
  4. ^ By Mark LaPedus, Semiconductor Engineering. “Fan-Out Packaging Gains Steam.” November 23, 2015. Retrieved May 23, 2016.
  5. ^ https://www.nxp.com/docs/en/application-note/AN3846.pdf
  6. ^ "Stats ChipPAC - Wafer Level CSP (WLCSP) - a FIWLP Technology". www.statschippac.com.
  7. ^ "WLCSP Overview, Market and Applications". November 11, 2018.
  8. ^ By Leon Spencer, ZDNet. “Raspberry Pi 2 power crashes when exposed to xenon flash.” February 9, 2015. Retrieved February 5, 2016.

Further reading[edit]

  • Shichun Qu; Yong Liu (2014). Wafer-Level Chip-Scale Packaging: Analog and Power Semiconductor Applications. Springer. ISBN 978-1-4939-1556-9.