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x2APIC is the most recent generation of the Intel programmable interrupt controller, introduced with the Nehalem microarchitecture[1] (November 2008). The major improvements of the x2APIC address the number of supported CPUs and performance of the interface.


The x2APIC now uses 32 bits to address CPUs, allowing to address up to 232 − 1 CPUs using the physical destination mode. The logical destination mode now works differently and introduces clusters; using this mode, one can address up to 220 − 16 processors. The x2APIC architecture also provides backward compatibility modes to the original Intel APIC Architecture (introduced with the Pentium/P6) and with the xAPIC architecture (introduced with the Pentium 4).

The improved interface reduces the number of needed APIC register access for sending Inter-processor interrupts (IPIs). Because of this advantage, QEMU can and does emulate x2APIC for older processors that do not physically support it, going back to Conroe and even for AMD Opteron G-series processors (neither of which natively support x2APIC).[2][3]

Virtualization-related developments[edit]

As of 2012 AMD does not yet support x2APIC, but was announcing the introduction of their own Advanced Virtual Interrupt Controller (AVIC) targeting interrupt overhead reduction in virtualization environments.[4][5]

Intel has responded with the announcement of a similar technology, which didn't have a brand name at its announcement time in 2012,[6] but which was later branded APICv[7][8] and is commercially available in the Ivy Bridge EP series, which is sold as Xeon E5-26xx v2 (launched in late 2013) and as Xeon E5-46xx v2 (launched in early 2014).

See also[edit]


External links[edit]