|Version||ARCHLVL 2 and ARCHLVL 3 (2008)|
|Encoding||Variable (2, 4 or 6 bytes long)|
|Branching||Condition code, indexing, counting|
|General purpose||16× 64-bit|
|Floating point||16× 64-bit (plus 32× 128-bit vector registers in latest version)|
|History of IBM mainframes, 1952–present|
z/Architecture, initially and briefly called ESA Modal Extensions (ESAME), is IBM's 64-bit instruction set architecture implemented by its mainframe computers. IBM introduced its first z/Architecture-based system, the z900, in late 2000. Later z/Architecture systems include the IBM z800, z990, z890, System z9, System z10, zEnterprise 196, and zEnterprise 114. z/Architecture retains backward compatibility with previous 32-bit-data/31-bit-addressing architecture ESA/390 and its predecessors all the way back to the 32-bit-data/24-bit-addressing System/360.
Most operating systems, including z/OS, generally restrict code execution to the first 2 GB (31 bits) of each virtual address space for reasons of efficiency and compatibility rather than architectural limits. The z/OS implementation of the Java programming language is an exception. The z/OS's virtual memory implementation supports multiple 2 GB address spaces, permitting more than 2 GB of concurrently resident program code. The 64-bit version of Linux on System z allows code to execute from 64-bit address ranges.
For programmers who need to store large amounts of data, the 64-bit address space usually suffices. If, however, they need more data than a 16 EB address space can hold, other extended addressability techniques allow programmers to extend their applications through the use of additional address spaces or data-only spaces. The data-only spaces that are available for user programs are called dataspaces and hiperspaces. These spaces are similar in that both are areas of virtual storage that your program can create. Their size can be up to 2 gigabytes, as your program requests. Unlike an address space, a dataspace or hiperspace contains only user data; it does not contain system control blocks or common areas. Program code cannot run in a dataspace or a hiperspace. A dataspace differs from a hiperspace in that dataspaces are byte-addressable whereas hiperspaces are page-addressable. The z/VSE Version 4, z/TPF Version 1 and z/VM Version 5 operating systems, and presumably their successors, require z/Architecture.
z/Architecture supports running multiple concurrent operating systems and applications even if they use different address sizes. This allows software developers to choose the address size that is most advantageous for their applications and data structures.
Platform Solutions Inc. (PSI) previously marketed Itanium-based servers which were compatible with z/Architecture. IBM bought PSI in July, 2008, and the PSI systems are no longer available. FLEX-ES, zPDT and the Hercules emulator also implement z/Architecture. Hitachi mainframes running newer releases of the VOS3 operating system implement ESA/390 plus Hitachi-unique CPU instructions, including a few 64-bit instructions. While Hitachi was likely inspired by z/Architecture (and formally collaborated with IBM on the z800 model, introduced in 2002), Hitachi's machines are not z/Architecture-compatible.
On July 7, 2009, IBM on occasion of announcing a new version of one of its operating systems implicitly stated that Architecture Level Set 4 (ALS 4) exists, and is implemented on the System z10 and subsequent machines. The ALS 4 is also specified in LOADxx as ARCHLVL 3, whereas the earlier z900, z800, z990, z890, System z9 specified ARCHLVL 2. Earlier announcements of System z10 simply specified that it implements z/Architecture with some additions: 50+ new machine instructions, 1 MB page frames, and hardware decimal floating point unit (HDFU).
- Development and Attributes of z/Architecture, IBM Journal of Research and Development, 2002.
- "IBM Acquires Platform Solutions" (Press release). IBM. 2008-07-02. Retrieved 2008-09-06.
- Preview: IBM z/VM V6.1 - Foundation for future virtualization growth, IBM United States Software Announcement 209-207, dated July 7, 2009
- ALS 1 was 9672 G2; ALS 2 was 9672 G5; ALS 3 was the original z/Architecture: "IBM CMOS Processor Table".
- "IBM System z10 Business Class (z10 BC) Reference Guide" (PDF). 2008.
- z/Architecture Principles of Operation