Zero instruction set computer
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In computer science, zero instruction set computer (ZISC) refers to a computer architecture based solely on pattern matching and absence of (micro-)instructions in the classical[clarification needed] sense. These chips are known for being thought of as comparable to the neural networks, being marketed for the number of "synapses" and "neurons".
ZISC is a technology[clarification needed] based on ideas[which?] from artificial neural networks and massively parallel processing. This concept[which?] was invented by Guy Paillet.
Their massively parallel computing solves the clarification needed from Winner-takes-all problem in Neural Networks] by allotting each "neuron" its own memory and allowing simultaneous problem-solving the results of which are settled up disputing with each other.[
Between 1993 and 2010, DARPA and Intel co-developed the NI1000 around the same time of IBM's patent.
In August 2007, the CM1K (CogniMem 1,024 neurons) was introduced by CogniMem Ltd. CM1K was designed by Anne Menendez and Guy Paillet.
Applications and controversy
According to TechCrunch, software emulations of these types of chips are currently used for image recognition by many large tech companies, such as Facebook and Google. When applied to other miscellaneous pattern detection tasks, such as with text, results are said to be produced in microseconds even with chips released in 2007.
Junko Yoshida, of the EE Times, compared the NeuroMem chip with "The Machine", a machine capable of being able to predict crimes from scanning people's faces, from Person of Interest (TV series) describing it as "the heart of big data" and "foreshadow[ing] a real-life escalation in the era of massive data collection".
- Lambinet, Philippe. "The Ongoing Quest For The 'Brain' Chip". TechCrunch.
- Higginbotham, Stacey. "Make way for more brain-based chips". Gigaom.
- "CogniMem Technologies Inc. Technology Background". Retrieved 2012-03-08.
- Yoshida, Junko. "NeuroMem IC Matches Patterns, Sees All, Knows All". EE Times.
- US Patent for ZISC hardware, issued to IBM/G.Paillet on April 15, 1997
- Image Processing Using RBF like Neural Networks: A ZISC-036 Based Fully Parallel Implementation Solving Real World and Real Complexity Industrial Problems by K. Madani, G. de Trémiolles, and P. Tannhof
- From CISC to RISC to ZISC by S. Liebman on lsmarketing.com
- Neural Networks on Silicon at aboutAI.net
- Zero instruction set computer at Curlie (based on DMOZ)
- NeuroMem CM1K chip, successor of the ZISC, designed by G.Paillet/General Vision
- CogniMem Technologies Inc. Massively Parallel Hardware Acceleration for Pattern Recognition
- ZISC genesis and succession