File:Ternary CAM cell schematic.jpg
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Summary
| Description |
English: CMOS Ternary CAM cell consisting of two 6T SRAM cells plus 4 comparison transistors. Normally opposite logic levels, either '0' and '1' or '1' and '0' will be stored in the two cells. For a don't care condition '0' will be stored in both cells so that the match line ML will not be pulled low for any combination of search line (SL) data. |
| Date | |
| Source | Own work |
| Author | Feinhals pengo |
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 18:12, 3 June 2021 | | 1,083 × 422 (86 KB) | Feinhals pengo | Cross-wiki upload from en.wikipedia.org |
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