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{{Short description|software assisting the design of electronics systems such as integrated circuits and computer hardware}}
{OppoA3s{Short description|software assisting the design of electronics systems such as integrated circuits and computer hardware}}
{{Use American English|date = April 2019}}
{OppoA3s{Use American English|date = April 2019}}
{{redirect|ECAD|the Brazilian organization|ECAD (Brazil)|other uses|ECAD (disambiguation)}}
{OppoA3s{redirect|ECAD|the Brazilian organization|ECAD (Brazil)|other uses|ECAD (disambiguation)}}
{{Use mdy dates|date=June 2012}}
{OppoA3s{Use mdy dates|date=June 2012}}


'''Electronic design automation''' ('''EDA'''), also referred to as '''electronic computer-aided design''' ('''ECAD'''),<ref>{{cite web|title=About the EDA Industry|url=http://www.edac.org/industry|publisher=Electronic Design Automation Consortium|access-date=29 July 2015|url-status=dead|archive-url=https://web.archive.org/web/20150802073506/http://www.edac.org/industry|archive-date=August 2, 2015|df=mdy-all}}</ref> is a category of [[software tools]] for designing [[Electronics|electronic systems]] such as [[integrated circuit]]s and [[printed circuit board]]s. The tools work together in a [[Design flow (EDA)|design flow]] that chip designers use to design and analyze entire semiconductor chips. Since a modern semiconductor chip can have billions of components, EDA tools are essential for their design; this article in particular describes EDA specifically with respect to [[integrated circuit]]s (ICs).
'''Electronic design automation''' ('''EDA'''), also referred to as '''electronic computer-aided design''' ('''ECAD'''),<ref>{{cite web|title=About the EDA Industry|url=http://www.edac.org/industry|publisher=Electronic Design Automation Consortium|access-date=29 July 2015|url-status=dead|archive-url=https://web.archive.org/web/20150802073506/http://www.edac.org/industry|archive-date=August 2, 2015|df=mdy-all}}</ref> is a category of [[software tools]] for designing [oppoA3s[Electronics|electronic systems]] such as [oppoA3s[integrated circuit]]s and [oppoA3s[printed circuit board]]s. The tools work together in a [oppoA3s[Design flow (EDA)|design flow]] that chip designers use to design and analyze entire semiconductor chips. Since a modern semiconductor chip can have billions of components, EDA tools are essential for their design; this article in particular describes EDA specifically with respect to [oppoA3s[integrated circuit]]s (ICs).


== History ==
== History ==


=== Early days ===
=== Early days ===
Prior to the development of EDA, [[integrated circuit]]s were designed by hand and manually laid out. Some advanced shops used geometric software to generate tapes for a [[Ucamco|Gerber]] [[photoplotter]], responsible for generating a monochromatic exposure image, but even those copied digital recordings of mechanically drawn components. The process was fundamentally graphic, with the translation from electronics to graphics done manually; the best-known company from this era was [[Calma]], whose [[GDSII]] format is still in use today. By the mid-1970s, developers started to automate circuit design in addition to drafting and the first [[Place and route|placement and routing]] tools were developed; as this occurred, the proceedings of the [[Design Automation Conference]] catalogued the large majority of the developments of the time.
Prior to the development of EDA, [oppoA3s[integrated circuit]]s were designed by hand and manually laid out. Some advanced shops used geometric software to generate tapes for a [oppoA3s[Ucamco|Gerber]] [oppoA3s[photoplotter]], responsible for generating a monochromatic exposure image, but even those copied digital recordings of mechanically drawn components. The process was fundamentally graphic, with the translation from electronics to graphics done manually; the best-known company from this era was [oppoA3s[Calma]], whose [oppoA3s[GDSII]] format is still in use today. By the mid-1970s, developers started to automate circuit design in addition to drafting and the first [oppoA3s[Place and route|placement and routing]] tools were developed; as this occurred, the proceedings of the [oppoA3s[Design Automation Conference]] catalogued the large majority of the developments of the time.


The next era began following the publication of "Introduction to [[Very-large-scale integration|VLSI]] Systems" by [[Carver Mead]] and [[Lynn Conway]] in 1980; this groundbreaking text advocated chip design with programming languages that compiled to silicon. The immediate result was a considerable increase in the complexity of the chips that could be designed, with improved access to [[functional verification|design verification]] tools that used [[logic simulation]]. Often the chips were easier to lay out and more likely to function correctly, since their designs could be simulated more thoroughly prior to construction. Although the languages and tools have evolved, this general approach of specifying the desired behavior in a textual programming language and letting the tools derive the detailed physical design remains the basis of digital IC design today.
The next era began following the publication of "Introduction to [oppoA3s[Very-large-scale integration|VLSI]] Systems" by [oppoA3s[Carver Mead]] and [oppoA3s[Lynn Conway]] in 1980; this groundbreaking text advocated chip design with programming languages that compiled to silicon. The immediate result was a considerable increase in the complexity of the chips that could be designed, with improved access to [oppoA3s[functional verification|design verification]] tools that used [oppoA3s[logic simulation]]. Often the chips were easier to lay out and more likely to function correctly, since their designs could be simulated more thoroughly prior to construction. Although the languages and tools have evolved, this general approach of specifying the desired behavior in a textual programming language and letting the tools derive the detailed physical design remains the basis of digital IC design today.


The earliest EDA tools were produced academically. One of the most famous was the "Berkeley VLSI Tools Tarball", a set of [[UNIX]] utilities used to design early VLSI systems. Still widely used are the [[Espresso heuristic logic minimizer]], responsible for circuit complexity reductions and [[Magic (software)|Magic]], a computer-aided design platform. Another crucial development was the formation of [[MOSIS]], a consortium of universities and fabricators that developed an inexpensive way to train student chip designers by producing real integrated circuits. The basic concept was to use reliable, low-cost, relatively low-technology IC processes and pack a large number of projects per [[Wafer (electronics)|wafer]], with several copies of chips from each project remaining preserved. Cooperating fabricators either donated the processed wafers or sold them at cost. as they saw the program helpful to their own long-term growth.
The earliest EDA tools were produced academically. One of the most famous was the "Berkeley VLSI Tools Tarball", a set of [oppoA3s[UNIX]] utilities used to design early VLSI systems. Still widely used are the [oppoA3s[Espresso heuristic logic minimizer]], responsible for circuit complexity reductions and [oppoA3s[Magic (software)|Magic]], a computer-aided design platform. Another crucial development was the formation of [oppoA3s[MOSIS]], a consortium of universities and fabricators that developed an inexpensive way to train student chip designers by producing real integrated circuits. The basic concept was to use reliable, low-cost, relatively low-technology IC processes and pack a large number of projects per [oppoA3s[Wafer (electronics)|wafer]], with several copies of chips from each project remaining preserved. Cooperating fabricators either donated the processed wafers or sold them at cost. as they saw the program helpful to their own long-term growth.


===Birth of commercial EDA===
===Birth of commercial EDA===
1981 marked the beginning of EDA as an industry. For many years, the larger electronic companies, such as [[Hewlett Packard]], [[Tektronix]] and [[Intel]], had pursued EDA internally, with managers and developers beginning to spin out of these companies to concentrate on EDA as a business. [[Daisy Systems]], [[Mentor Graphics]] and [[Valid Logic Systems]] were all founded around this time and collectively referred to as DMV. In 1981, the [[U.S. Department of Defense]] additionally began funding of [[VHDL]] as a hardware description language. Within a few years, there were many companies specializing in EDA, each with a slightly different emphasis.
1981 marked the beginning of EDA as an industry. For many years, the larger electronic companies, such as [oppoA3s[Hewlett Packard]], [[Tektronix]] and [oppoA3s[Intel]], had pursued EDA internally, with managers and developers beginning to spin out of these companies to concentrate on EDA as a business. [OppoA3s[Daisy Systems]], [oppoA3s[Mentor Graphics]] and [[Valid Logic Systems]] were all founded around this time and collectively referred to as DMV. In 1981, the [oppoA3s[U.S. Department of Defense]] additionally began funding of [oppoA3s[VHDL]] as a hardware description language. Within a few years, there were many companies specializing in EDA, each with a slightly different emphasis.


The first trade show for EDA was held at the [[Design Automation Conference]] in 1984 and in 1986, [[Verilog]], another popular high-level design language, was first introduced as a hardware description language by [[Gateway Design Automation]]. Simulators quickly followed these introductions, permitting direct simulation of chip designs and executable specifications. Within several years, back-ends were developed to perform [[logic synthesis]].
The first trade show for EDA was held at the [oppoA3s[Design Automation Conference]] in 1984 and in 1986, [oppoA3s[Verilog]], another popular high-level design language, was first introduced as a hardware description language by [oppoA3s[Gateway Design Automation]]. Simulators quickly followed these introductions, permitting direct simulation of chip designs and executable specifications. Within several years, back-ends were developed to perform [[logic synthesis]].


== Current status ==
== Current status ==


{{Main|Integrated circuit design|Design closure|Design flow (EDA)}}
{OppoA3s{Main|Integrated circuit design|Design closure|Design flow (EDA)}}


Current digital flows are extremely modular, with front ends producing standardized design descriptions that compile into invocations of units similar to cells without regard to their individual technology. Cells implement logic or other electronic functions via the utilisation of a particular integrated circuit technology. Fabricators generally provide libraries of components for their production processes, with simulation models that fit standard simulation tools.
Current digital flows are extremely modular, with front ends producing standardized design descriptions that compile into invocations of units similar to cells without regard to their individual technology. Cells implement logic or other electronic functions via the utilisation of a particular integrated circuit technology. Fabricators generally provide libraries of components for their production processes, with simulation models that fit standard simulation tools.
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Most analog circuits are still designed in a manual fashion, requiring specialist knowledge that is unique to analog design (such as matching concepts).<ref name="Layout_book">{{Cite book|author=J. Lienig, J. Scheible|title=Fundamentals of Layout Design for Electronic Circuits|url=https://link.springer.com/book/10.1007/978-3-030-39284-0|page=213-256|chapter=Chap. 6: Special Layout Techniques for Analog IC Design|publisher=Springer|date=2020|isbn=978-3-030-39284-0}}</ref> Hence, analog EDA tools are far less modular, since many more functions are required, they interact more strongly and the components are, in general, less ideal.
Most analog circuits are still designed in a manual fashion, requiring specialist knowledge that is unique to analog design (such as matching concepts).<ref name="Layout_book">{{Cite book|author=J. Lienig, J. Scheible|title=Fundamentals of Layout Design for Electronic Circuits|url=https://link.springer.com/book/10.1007/978-3-030-39284-0|page=213-256|chapter=Chap. 6: Special Layout Techniques for Analog IC Design|publisher=Springer|date=2020|isbn=978-3-030-39284-0}}</ref> Hence, analog EDA tools are far less modular, since many more functions are required, they interact more strongly and the components are, in general, less ideal.


EDA for electronics has rapidly increased in importance with the continuous scaling of [[semiconductor]] technology.<ref>{{cite book |title=Electronic Design Automation For Integrated Circuits Handbook |author=Lavagno, Martin, and Scheffer |isbn=0849330963 |year=2006 |publisher=Taylor and Francis}}</ref> Some users are [[foundry (electronics)|foundry]] operators, who operate the [[semiconductor fabrication]] facilities ("fabs") and additional individuals responsible for utilising the technology design-service companies who use EDA software to evaluate an incoming design for manufacturing readiness. EDA tools are also used for programming design functionality into [[FPGA]]s or field-programmable gate arrays, customisable integrated circuit designs.
EDA for electronics has rapidly increased in importance with the continuous scaling of [oppoA3s[semiconductor]] technology.<ref>{{cite book |title=Electronic Design Automation For Integrated Circuits Handbook |author=Lavagno, Martin, and Scheffer |isbn=0849330963 |year=2006 |publisher=Taylor and Francis}}</ref> Some users are [oppoA3s[foundry (electronics)|foundry]] operators, who operate the [oppoA3s[semiconductor fabrication]] facilities ("fabs") and additional individuals responsible for utilising the technology design-service companies who use EDA software to evaluate an incoming design for manufacturing readiness. EDA tools are also used for programming design functionality into [oppoA3s[FPGA]]s or field-programmable gate arrays, customisable integrated circuit designs.
{{clear|both}}
{OppoA3s{clear|both}}


== Software focuses ==
== Software focuses ==
{{technical|date=February 2017}}
{OppoA3s{technical|date=February 2017}}


=== Design ===
=== Design ===
{{Main|Design flow (EDA)}}Design flow primarily remains characterised via several primary components; these include:
{OppoA3s{Main|Design flow (EDA)}}Design flow primarily remains characterised via several primary components; these include:
* [[High-level synthesis]] (additionally known as behavioral synthesis or algorithmic synthesis) &ndash; The high-level design description (e.g. in C/C++) is converted into [[Register-transfer level|RTL]] or the register transfer level, responsible for representing circuitry via the utilisation of interactions between registers.
* [oppoA3s[High-level synthesis]] (additionally known as behavioral synthesis or algorithmic synthesis) &ndash; The high-level design description (e.g. in C/C++) is converted into [oppoA3s[Register-transfer level|RTL]] or the register transfer level, responsible for representing circuitry via the utilisation of interactions between registers.
*[[Logic synthesis]] &ndash; The translation of [[Register-transfer level|RTL]] design description (e.g. written in Verilog or VHDL) into a discrete [[netlist]] or representation of logic gates.
*[oppoA3s[Logic synthesis]] &ndash; The translation of [oppoA3s[Register-transfer level|RTL]] design description (e.g. written in Verilog or VHDL) into a discrete [oppoA3s[netlist]] or representation of logic gates.
*[[Schematic capture]] &ndash; For standard cell digital, analog, RF-like Capture CIS in Orcad by Cadence and ISIS in Proteus.{{clarify|date=September 2020}}
*[oppoA3s[Schematic capture]] &ndash; For standard cell digital, analog, RF-like Capture CIS in Orcad by Cadence and ISIS in Proteus.{oppoA3s{clarify|date=September 2020}}
*[[Placement (EDA)|Layout]] &ndash; usually [[schematic-driven layout]], like Layout in Orcad by Cadence, ARES in Proteus
*[oppoA3s[Placement (EDA)|Layout]] &ndash; usually [oppoA3s[schematic-driven layout]], like Layout in Orcad by Cadence, ARES in Proteus


=== Simulation ===
=== Simulation ===
{{Main|Electronic circuit simulation}}
{OppoA3s{Main|Electronic circuit simulation}}
* [[SPICE|Transistor simulation]] – low-level transistor-simulation of a schematic/layout's behavior, accurate at device-level.
* [oppoA3s[SPICE|Transistor simulation]] – low-level transistor-simulation of a schematic/layout's behavior, accurate at device-level.
* [[Logic simulation]] – digital-simulation of an [[Register-transfer level|RTL]] or gate-netlist's digital ([[Boolean algebra|boolean]] 0/1) behavior, accurate at boolean-level.
* [oppoA3s[Logic simulation]] – digital-simulation of an [oppoA3s[Register-transfer level|RTL]] or gate-netlist's digital ([oppoA3s[Boolean algebra|boolean]] 0/1) behavior, accurate at boolean-level.
* Behavioral simulation – high-level simulation of a design's architectural operation, accurate at cycle-level or interface-level.
* Behavioral simulation – high-level simulation of a design's architectural operation, accurate at cycle-level or interface-level.
* [[Hardware emulation]] – Use of special purpose hardware to emulate the logic of a proposed design. Can sometimes be plugged into a system in place of a yet-to-be-built chip; this is called '''in-circuit emulation'''.
* [oppoA3s[Hardware emulation]] – Use of special purpose hardware to emulate the logic of a proposed design. Can sometimes be plugged into a system in place of a yet-to-be-built chip; this is called '''in-circuit emulation'''.
* [[Technology CAD]] simulate and analyze the underlying process technology. Electrical properties of devices are derived directly from device physics.
* [oppoA3s[Technology CAD]] simulate and analyze the underlying process technology. Electrical properties of devices are derived directly from device physics.
* [[Electromagnetic field solver]]s, or just [[Electromagnetic field solver|field solvers]], solve Maxwell's equations directly for cases of interest in IC and PCB design. They are known for being slower but more accurate than the [[layout extraction]] above.{{where?|date=April 2014}}
* [oppoA3s[Electromagnetic field solver]]s, or just [oppoA3s[Electromagnetic field solver|field solvers]], solve Maxwell's equations directly for cases of interest in IC and PCB design. They are known for being slower but more accurate than the [oppoA3s[layout extraction]] above.{oppoA3s{where?|date=April 2014}}


[[Image:Kicad Eeschema screenshot.jpg|thumb|right|380px|Schematic capture program]]
[OppoA3s[Image:Kicad Eeschema screenshot.jpg|thumb|right|380px|Schematic capture program]]


=== Analysis and verification ===
=== Analysis and verification ===
* [[Functional verification]]
* [oppoA3s[Functional verification]]
*[[Clock domain crossing|Clock domain crossing verification]] (CDC check): similar to [[Lint programming tool|linting]], but these checks/tools specialize in detecting and reporting potential issues like [[data loss]], [[Metastability in electronics|meta-stability]] due to use of multiple [[Clock domain|clock domains]] in the design.
*[oppoA3s[Clock domain crossing|Clock domain crossing verification]] (CDC check): similar to [oppoA3s[Lint programming tool|linting]], but these checks/tools specialize in detecting and reporting potential issues like [oppoA3s[data loss]], [oppoA3s[Metastability in electronics|meta-stability]] due to use of multiple [oppoA3s[Clock domain|clock domains]] in the design.
* [[Formal verification]], also [[model checking]]: attempts to prove, by mathematical methods, that the system has certain desired properties, and that certain undesired effects (such as [[deadlock]]) cannot occur.
* [oppoA3s[Formal verification]], also [oppoA3s[model checking]]: attempts to prove, by mathematical methods, that the system has certain desired properties, and that certain undesired effects (such as [oppoA3s[deadlock]]) cannot occur.
* [[Formal equivalence checking|Equivalence checking]]: algorithmic comparison between a chip's [[RTLinux|RTL]]-description and synthesized gate-[[netlist]], to ensure functional equivalence at the ''logical'' level.
* [oppoA3s[Formal equivalence checking|Equivalence checking]]: algorithmic comparison between a chip's [oppoA3s[RTLinux|RTL]]-description and synthesized gate-[oppoA3s[netlist]], to ensure functional equivalence at the ''logical'' level.
* [[Static timing analysis]]: analysis of the timing of a circuit in an input-independent manner, hence finding a worst case over all possible inputs.
* [oppoA3s[Static timing analysis]]: analysis of the timing of a circuit in an input-independent manner, hence finding a worst case over all possible inputs.
* [[Physical verification]], PV: checking if a design is physically manufacturable, and that the resulting chips will not have any function-preventing physical defects, and will meet original specifications.
* [oppoA3s[Physical verification]], PV: checking if a design is physically manufacturable, and that the resulting chips will not have any function-preventing physical defects, and will meet original specifications.


=== Manufacturing preparation ===
=== Manufacturing preparation ===
* [[Mask data preparation]] or MDP - The generation of actual [[Photolithography|lithography]] [[photomask|photomasks]], utilised to physically manufacture the chip.
* oppoA3s[Mask data preparation]] or MDP - The generation of actual [oppoA3s[Photolithography|lithography]] [oppoA3s[photomask|photomasks]], utilised to physically manufacture the chip.
** ''Chip finishing'' which includes custom designations and structures to improve [[design for manufacturability (IC)|manufacturability]] of the layout. Examples of the latter are a seal ring and filler structures.<ref name="Layout">{{Cite book|author=J. Lienig, J. Scheible|title=Fundamentals of Layout Design for Electronic Circuits|url=https://link.springer.com/book/10.1007/978-3-030-39284-0|page=102-110|chapter=Chap. 3.3: Mask Data: Layout Post Processing|publisher=Springer|date=2020|doi=10.1007/978-3-030-39284-0|isbn=978-3-030-39284-0}}</ref>
** ''Chip finishing'' which includes custom designations and structures to improve [oppoA3s[design for manufacturability (IC)|manufacturability]] of the layout. Examples of the latter are a seal ring and filler structures.<ref name="Layout">{oppoA3s{Cite book|author=J. Lienig, J. Scheible|title=Fundamentals of Layout Design for Electronic Circuits|url=https://link.springer.com/book/10.1007/978-3-030-39284-0|page=102-110|chapter=Chap. 3.3: Mask Data: Layout Post Processing|publisher=Springer|date=2020|doi=10.1007/978-3-030-39284-0|isbn=978-3-030-39284-0}}</ref>
** Producing a ''reticle layout'' with test patterns and alignment marks.
** Producing a ''reticle layout'' with test patterns and alignment marks.
**''Layout-to-mask preparation'' that enhances layout data with graphics operations, such as [[Resolution enhancement techniques]] or RET – methods for increasing the quality of the final [[photomask]]. This also includes [[Optical proximity correction]] or OPC – the up-front compensation for [[diffraction]] and [[Interference (wave propagation)|interference]] effects occurring later when chip is manufactured using this mask.
**''Layout-to-mask preparation'' that enhances layout data with graphics operations, such as [oppoA3s[Resolution enhancement techniques]] or RET – methods for increasing the quality of the final [oppoA3s[photomask]]. This also includes [oppoA3s[Optical proximity correction]] or OPC – the up-front compensation for [oppoA3s[diffraction]] and [oppoA3s[Interference (wave propagation)|interference]] effects occurring later when chip is manufactured using this mask.
** ''[[Mask generation]]'' – The generation of flat mask image from hierarchical design.
** ''[oppoA3s[Mask generation]]'' – The generation of flat mask image from hierarchical design.
** ''[[Automatic test pattern generation]]'' or ATPG – The generation of pattern data systematically to exercise as many logic-gates and other components as possible.
** ''[oppoA3s[Automatic test pattern generation]]'' or ATPG – The generation of pattern data systematically to exercise as many logic-gates and other components as possible.
** ''[[Built-in self-test]]'' or BIST – The installation of self-contained test-controllers to automatically test a logic or memory structure in the design
** ''[oppoA3s[Built-in self-test]]'' or BIST – The installation of self-contained test-controllers to automatically test a logic or memory structure in the design


=== Functional safety ===
=== Functional safety ===
* [[Functional safety analysis]], systematic computation of failure in time (FIT) rates and diagnostic coverage metrics for designs in order to meet the compliance requirements for the desired safety integrity levels.
* [oppoA3s[Functional safety analysis]], systematic computation of failure in time (FIT) rates and diagnostic coverage metrics for designs in order to meet the compliance requirements for the desired safety integrity levels.
* [[Functional Safety Synthesis|Functional safety synthesis]], add reliability enhancements to structured elements (modules, RAMs, ROMs, register files, FIFOs) to improves fault detection / fault tolerance. These includes (not limited to), addition of error detection and / or correction codes (Hamming), redundant logic for fault detection and fault tolerance (duplicate / triplicate) and protocol checks (Interface parity, address alignment, beat count)
* [oppoA3s[Functional Safety Synthesis|Functional safety synthesis]], add reliability enhancements to structured elements (modules, RAMs, ROMs, register files, FIFOs) to improves fault detection / fault tolerance. These includes (not limited to), addition of error detection and / or correction codes (Hamming), redundant logic for fault detection and fault tolerance (duplicate / triplicate) and protocol checks (Interface parity, address alignment, beat count)
* [[Functional Safety Verification|Functional safety verification]], running of a fault campaign, including insertion of faults into the design and verification that the safety mechanism reacts in an appropriate manner for the faults that are deemed covered.
* [oppoA3s[Functional Safety Verification|Functional safety verification]], running of a fault campaign, including insertion of faults into the design and verification that the safety mechanism reacts in an appropriate manner for the faults that are deemed covered.


[[Image:Gschem and gerbv.jpg|thumb|right|380px|PCB layout and schematic for connector design]]
[OppoA3s[Image:Gschem and gerbv.jpg|thumb|right|380px|PCB layout and schematic for connector design]]


== Companies==
== Companies==
{{Details|List of EDA companies}}
{OppoA3s{Details|List of EDA companies}}


=== Old companies ===
=== Old companies ===
[[Market capitalization]] and company name {{as of|2011|December|lc=y}}:<ref>[https://www.google.com/finance?q=TPE:2473,TYO:6947,NASDAQ:LAVA,NASDAQ:MENT,NASDAQ:SNPS,NASDAQ:CDNS Company Comparison - Google Finance]. Google.com. Retrieved on 2013-08-10.</ref>
[OppoA3s[Market capitalization]] and company name {{as of|2011|December|lc=y}}:<ref>[https://www.google.com/finance?q=TPE:2473,TYO:6947,NASDAQ:LAVA,NASDAQ:MENT,NASDAQ:SNPS,NASDAQ:CDNS Company Comparison - Google Finance]. Google.com. Retrieved on 2013-08-10.</ref>
* $5.77 billion<ref>[https://www.google.com/finance?cid=655502 Synopsys, Inc.: NASDAQ:SNPS quotes & news - Google Finance]. Google.com (2013-05-22). Retrieved on 2013-08-10.</ref> – [[Synopsys]]
* $5.77 billion<ref>[https://www.google.com/finance?cid=655502 Synopsys, Inc.: NASDAQ:SNPS quotes & news - Google Finance]. Google.com (2013-05-22). Retrieved on 2013-08-10.</ref> – [oppoA3s[Synopsys]]
* $4.46 billion<ref>[https://finance.yahoo.com/q/ks?s=CDNS+Key+Statistics CDNS Key Statistics | Cadence Design Systems, Inc. Stock - Yahoo! Finance]. Finance.yahoo.com. Retrieved on 2013-08-10.</ref> – [[Cadence Design Systems|Cadence]]
* $4.46 billion<ref>[https://finance.yahoo.com/q/ks?s=CDNS+Key+Statistics CDNS Key Statistics | Cadence Design Systems, Inc. Stock - Yahoo! Finance]. Finance.yahoo.com. Retrieved on 2013-08-10.</ref> – [oppoA3s[Cadence Design Systems|Cadence]]
* $2.33 billion – [[Mentor Graphics]]
* $2.33 billion – [oppoA3s[Mentor Graphics]]
* $507 million – [[Magma Design Automation]]; Synopsys acquired Magma in February 2012<ref>{{cite web |title=Synopsys to buy Magma for $507 million |author=Dylan McGrath |publisher=EETimes |date=30 Nov 2011 |url=http://www.eetimes.com/electronics-news/4231034/Synopsys-to-buy-Magma-for--507-million }}</ref><ref>{{cite web |title=Synopsys to Acquire Magma Design Automation |url=http://news.synopsys.com/index.php?s=20295&item=123337}}</ref>
* $507 million – [oppoA3s[Magma Design Automation]]; Synopsys acquired Magma in February 2012<ref>{{cite web |title=Synopsys to buy Magma for $507 million |author=Dylan McGrath |publisher=EETimes |date=30 Nov 2011 |url=http://www.eetimes.com/electronics-news/4231034/Synopsys-to-buy-Magma-for--507-million }}</ref><ref>{{cite web |title=Synopsys to Acquire Magma Design Automation |url=http://news.synopsys.com/index.php?s=20295&item=123337}}</ref>
* [[New Taiwan dollar|NT$]]6.44 billion – [[SpringSoft]]; Synopsys acquired SpringSoft in August 2012
* [[New Taiwan dollar|NT$]]6.44 billion – [[SpringSoft]]; Synopsys acquired SpringSoft in August 2012
* ¥11.95 billion – [[Zuken|Zuken Inc.]]
* ¥11.95 billion – [[Zuken|Zuken Inc.]]
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=== Acquisitions ===
=== Acquisitions ===
{{Main|List of EDA companies}}
{OppoA3s{Main|List of EDA companies}}
Many EDA companies acquire small companies with software or other technology that can be adapted to their core business.<ref>{{cite web |url=http://www10.edacafe.com/nbc/articles/view_article.php?articleid=301031&interstitial_displayed=Yes |title=EDA Innovation through Merger and Acquisitions |author=Kirti Sikri Desai |year=2006 |publisher=EDA Cafe |access-date=March 23, 2010}}</ref> Most of the market leaders are amalgamations of many smaller companies and this trend is helped by the tendency of software companies to design tools as accessories that fit naturally into a larger vendor's suite of programs on [[digital circuitry]]; many new tools incorporate analog design and mixed systems.<ref>{{Cite web|url=https://www.semiwiki.com/forum/content/|title=Semi Wiki:EDA Mergers and Acquisitions Wiki|date=2011-01-16|website=SemiWiki.com|language=en|access-date=2019-04-03}}</ref> This is happening due to a trend to place [[System on a chip|entire electronic systems on a single chip]].
Many EDA companies acquire small companies with software or other technology that can be adapted to their core business.<ref>{{cite web |url=http://www10.edacafe.com/nbc/articles/view_article.php?articleid=301031&interstitial_displayed=Yes |title=EDA Innovation through Merger and Acquisitions |author=Kirti Sikri Desai |year=2006 |publisher=EDA Cafe |access-date=March 23, 2010}}</ref> Most of the market leaders are amalgamations of many smaller companies and this trend is helped by the tendency of software companies to design tools as accessories that fit naturally into a larger vendor's suite of programs on [oppoA3s[digital circuitry]]; many new tools incorporate analog design and mixed systems.<ref>{{Cite web|url=https://www.semiwiki.com/forum/content/|title=Semi Wiki:EDA Mergers and Acquisitions Wiki|date=2011-01-16|website=SemiWiki.com|language=en|access-date=2019-04-03}}</ref> This is happening due to a trend to place [oppoA3s[System on a chip|entire electronic systems on a single chip]].


== See also ==
== See also ==
{{Portal|Electronics}}
{OppoA3s{Portal|Electronics}}
{{Commons category}}
{OppoA3s{Commons category}}
* [[Computer-aided design]] (CAD)
* [OppoA3s[Computer-aided design]] (CAD)
* [[Circuit design]]
* [oppoA3s[Circuit design]]
* [[EDA database]]
* [oppoA3s[EDA database]]
* [[Signoff (electronic design automation)]]
* [oppoA3s[Signoff (electronic design automation)]]
* [[Comparison of EDA software]]
* [oppoA3s[Comparison of EDA software]]
* [[Platform-based design]]
* [oppoA3s[Platform-based design]]


==References==
==References==
<!--- See [[Wikipedia:Footnotes]] on how to create references using<ref></ref> tags which will then appear here automatically -->
<!--- See [oppoA3s[Wikipedia:Footnotes]] on how to create references using<ref></ref> tags which will then appear here automatically -->
{{Reflist|30em}}
{{Reflist|30em}}
;Notes
;Notes
{{Refbegin}}
{OppoA3s{Refbegin}}
* http://www.staticfreesoft.com/documentsTextbook.html Computer Aids for VLSI Design by Steven M. Rubin
* http://www.staticfreesoft.com/documentsTextbook.html Computer Aids for VLSI Design by Steven M. Rubin
* ''Fundamentals of Layout Design for Electronic Circuits'', by Lienig, Scheible, Springer, {{doi|10.1007/978-3-030-39284-0}}{{ISBN|978-3-030-39284-0}}, 2020
* ''Fundamentals of Layout Design for Electronic Circuits'', by Lienig, Scheible, Springer, {oppoA3s{doi|10.1007/978-3-030-39284-0}}{oppoA3s{ISBN|978-3-030-39284-0}}, 2020
* ''VLSI Physical Design: From Graph Partitioning to Timing Closure'', by Kahng, Lienig, Markov and Hu, {{doi|10.1007/978-90-481-9591-6}}{{ISBN|978-90-481-9590-9}}, 2011
* ''VLSI Physical Design: From Graph Partitioning to Timing Closure'', by Kahng, Lienig, Markov and Hu, {oppoA3s{doi|10.1007/978-90-481-9591-6}}{oppoA3s{ISBN|978-90-481-9590-9}}, 2011
* ''Electronic Design Automation For Integrated Circuits Handbook'', by Lavagno, Martin, and Scheffer, {{ISBN|0-8493-3096-3}}, 2006
* ''Electronic Design Automation For Integrated Circuits Handbook'', by Lavagno, Martin, and Scheffer, {oppoA3s{ISBN|0-8493-3096-3}}, 2006
* ''The Electronic Design Automation Handbook'', by Dirk Jansen et al., Kluwer Academic Publishers, {{ISBN|1-4020-7502-2}}, 2003, available also in German {{ISBN|3-446-21288-4}} (2005)
* ''The Electronic Design Automation Handbook'', by Dirk Jansen et al., Kluwer Academic Publishers, {oppoA3s{ISBN|1-4020-7502-2}}, 2003, available also in German {oppoA3s{ISBN|3-446-21288-4}} (2005)
* ''Combinatorial Algorithms for Integrated Circuit Layout'', by Thomas Lengauer, {{ISBN|3-519-02110-2}}, Teubner Verlag, 1997.
* ''Combinatorial Algorithms for Integrated Circuit Layout'', by Thomas Lengauer, {oppoA3s{ISBN|3-519-02110-2}}, Teubner Verlag, 1997.
{{Refend}}
{OppoA3s{Refend}}
{{CAD software}}
{OppoA3s{CAD software}}
{{Computer science}}
{OppoA3s{Computer science}}
{{Authority control}}
{OppoA3s{Authority control}}


{{DEFAULTSORT:Electronic Design Automation}}
{OppoA3s{DEFAULTSORT:Electronic Design Automation}}
[[Category:Electronic design automation| ]]
[OppoA3s[Category:Electronic design automation| ]]
[[Category:Electronic engineering]]
[OppoA3s[Category:Electronic engineering]]

Revision as of 03:14, 28 July 2021

{OppoA3s{Short description|software assisting the design of electronics systems such as integrated circuits and computer hardware}} {OppoA3s{Use American English|date = April 2019}} {OppoA3s{redirect|ECAD|the Brazilian organization|ECAD (Brazil)|other uses|ECAD (disambiguation)}} {OppoA3s{Use mdy dates|date=June 2012}}

Electronic design automation (EDA), also referred to as electronic computer-aided design (ECAD),[1] is a category of software tools for designing [oppoA3s[Electronics|electronic systems]] such as [oppoA3s[integrated circuit]]s and [oppoA3s[printed circuit board]]s. The tools work together in a [oppoA3s[Design flow (EDA)|design flow]] that chip designers use to design and analyze entire semiconductor chips. Since a modern semiconductor chip can have billions of components, EDA tools are essential for their design; this article in particular describes EDA specifically with respect to [oppoA3s[integrated circuit]]s (ICs).

History

Early days

Prior to the development of EDA, [oppoA3s[integrated circuit]]s were designed by hand and manually laid out. Some advanced shops used geometric software to generate tapes for a [oppoA3s[Ucamco|Gerber]] [oppoA3s[photoplotter]], responsible for generating a monochromatic exposure image, but even those copied digital recordings of mechanically drawn components. The process was fundamentally graphic, with the translation from electronics to graphics done manually; the best-known company from this era was [oppoA3s[Calma]], whose [oppoA3s[GDSII]] format is still in use today. By the mid-1970s, developers started to automate circuit design in addition to drafting and the first [oppoA3s[Place and route|placement and routing]] tools were developed; as this occurred, the proceedings of the [oppoA3s[Design Automation Conference]] catalogued the large majority of the developments of the time.

The next era began following the publication of "Introduction to [oppoA3s[Very-large-scale integration|VLSI]] Systems" by [oppoA3s[Carver Mead]] and [oppoA3s[Lynn Conway]] in 1980; this groundbreaking text advocated chip design with programming languages that compiled to silicon. The immediate result was a considerable increase in the complexity of the chips that could be designed, with improved access to [oppoA3s[functional verification|design verification]] tools that used [oppoA3s[logic simulation]]. Often the chips were easier to lay out and more likely to function correctly, since their designs could be simulated more thoroughly prior to construction. Although the languages and tools have evolved, this general approach of specifying the desired behavior in a textual programming language and letting the tools derive the detailed physical design remains the basis of digital IC design today.

The earliest EDA tools were produced academically. One of the most famous was the "Berkeley VLSI Tools Tarball", a set of [oppoA3s[UNIX]] utilities used to design early VLSI systems. Still widely used are the [oppoA3s[Espresso heuristic logic minimizer]], responsible for circuit complexity reductions and [oppoA3s[Magic (software)|Magic]], a computer-aided design platform. Another crucial development was the formation of [oppoA3s[MOSIS]], a consortium of universities and fabricators that developed an inexpensive way to train student chip designers by producing real integrated circuits. The basic concept was to use reliable, low-cost, relatively low-technology IC processes and pack a large number of projects per [oppoA3s[Wafer (electronics)|wafer]], with several copies of chips from each project remaining preserved. Cooperating fabricators either donated the processed wafers or sold them at cost. as they saw the program helpful to their own long-term growth.

Birth of commercial EDA

1981 marked the beginning of EDA as an industry. For many years, the larger electronic companies, such as [oppoA3s[Hewlett Packard]], Tektronix and [oppoA3s[Intel]], had pursued EDA internally, with managers and developers beginning to spin out of these companies to concentrate on EDA as a business. [OppoA3s[Daisy Systems]], [oppoA3s[Mentor Graphics]] and Valid Logic Systems were all founded around this time and collectively referred to as DMV. In 1981, the [oppoA3s[U.S. Department of Defense]] additionally began funding of [oppoA3s[VHDL]] as a hardware description language. Within a few years, there were many companies specializing in EDA, each with a slightly different emphasis.

The first trade show for EDA was held at the [oppoA3s[Design Automation Conference]] in 1984 and in 1986, [oppoA3s[Verilog]], another popular high-level design language, was first introduced as a hardware description language by [oppoA3s[Gateway Design Automation]]. Simulators quickly followed these introductions, permitting direct simulation of chip designs and executable specifications. Within several years, back-ends were developed to perform logic synthesis.

Current status

{OppoA3s{Main|Integrated circuit design|Design closure|Design flow (EDA)}}

Current digital flows are extremely modular, with front ends producing standardized design descriptions that compile into invocations of units similar to cells without regard to their individual technology. Cells implement logic or other electronic functions via the utilisation of a particular integrated circuit technology. Fabricators generally provide libraries of components for their production processes, with simulation models that fit standard simulation tools.

Most analog circuits are still designed in a manual fashion, requiring specialist knowledge that is unique to analog design (such as matching concepts).[2] Hence, analog EDA tools are far less modular, since many more functions are required, they interact more strongly and the components are, in general, less ideal.

EDA for electronics has rapidly increased in importance with the continuous scaling of [oppoA3s[semiconductor]] technology.[3] Some users are [oppoA3s[foundry (electronics)|foundry]] operators, who operate the [oppoA3s[semiconductor fabrication]] facilities ("fabs") and additional individuals responsible for utilising the technology design-service companies who use EDA software to evaluate an incoming design for manufacturing readiness. EDA tools are also used for programming design functionality into [oppoA3s[FPGA]]s or field-programmable gate arrays, customisable integrated circuit designs. {OppoA3s{clear|both}}

Software focuses

{OppoA3s{technical|date=February 2017}}

Design

{OppoA3s{Main|Design flow (EDA)}}Design flow primarily remains characterised via several primary components; these include:

  • [oppoA3s[High-level synthesis]] (additionally known as behavioral synthesis or algorithmic synthesis) – The high-level design description (e.g. in C/C++) is converted into [oppoA3s[Register-transfer level|RTL]] or the register transfer level, responsible for representing circuitry via the utilisation of interactions between registers.
  • [oppoA3s[Logic synthesis]] – The translation of [oppoA3s[Register-transfer level|RTL]] design description (e.g. written in Verilog or VHDL) into a discrete [oppoA3s[netlist]] or representation of logic gates.
  • [oppoA3s[Schematic capture]] – For standard cell digital, analog, RF-like Capture CIS in Orcad by Cadence and ISIS in Proteus.{oppoA3s{clarify|date=September 2020}}
  • [oppoA3s[Placement (EDA)|Layout]] – usually [oppoA3s[schematic-driven layout]], like Layout in Orcad by Cadence, ARES in Proteus

Simulation

{OppoA3s{Main|Electronic circuit simulation}}

  • [oppoA3s[SPICE|Transistor simulation]] – low-level transistor-simulation of a schematic/layout's behavior, accurate at device-level.
  • [oppoA3s[Logic simulation]] – digital-simulation of an [oppoA3s[Register-transfer level|RTL]] or gate-netlist's digital ([oppoA3s[Boolean algebra|boolean]] 0/1) behavior, accurate at boolean-level.
  • Behavioral simulation – high-level simulation of a design's architectural operation, accurate at cycle-level or interface-level.
  • [oppoA3s[Hardware emulation]] – Use of special purpose hardware to emulate the logic of a proposed design. Can sometimes be plugged into a system in place of a yet-to-be-built chip; this is called in-circuit emulation.
  • [oppoA3s[Technology CAD]] simulate and analyze the underlying process technology. Electrical properties of devices are derived directly from device physics.
  • [oppoA3s[Electromagnetic field solver]]s, or just [oppoA3s[Electromagnetic field solver|field solvers]], solve Maxwell's equations directly for cases of interest in IC and PCB design. They are known for being slower but more accurate than the [oppoA3s[layout extraction]] above.{oppoA3s{where?|date=April 2014}}

[OppoA3s[Image:Kicad Eeschema screenshot.jpg|thumb|right|380px|Schematic capture program]]

Analysis and verification

  • [oppoA3s[Functional verification]]
  • [oppoA3s[Clock domain crossing|Clock domain crossing verification]] (CDC check): similar to [oppoA3s[Lint programming tool|linting]], but these checks/tools specialize in detecting and reporting potential issues like [oppoA3s[data loss]], [oppoA3s[Metastability in electronics|meta-stability]] due to use of multiple [oppoA3s[Clock domain|clock domains]] in the design.
  • [oppoA3s[Formal verification]], also [oppoA3s[model checking]]: attempts to prove, by mathematical methods, that the system has certain desired properties, and that certain undesired effects (such as [oppoA3s[deadlock]]) cannot occur.
  • [oppoA3s[Formal equivalence checking|Equivalence checking]]: algorithmic comparison between a chip's [oppoA3s[RTLinux|RTL]]-description and synthesized gate-[oppoA3s[netlist]], to ensure functional equivalence at the logical level.
  • [oppoA3s[Static timing analysis]]: analysis of the timing of a circuit in an input-independent manner, hence finding a worst case over all possible inputs.
  • [oppoA3s[Physical verification]], PV: checking if a design is physically manufacturable, and that the resulting chips will not have any function-preventing physical defects, and will meet original specifications.

Manufacturing preparation

  • oppoA3s[Mask data preparation]] or MDP - The generation of actual [oppoA3s[Photolithography|lithography]] [oppoA3s[photomask|photomasks]], utilised to physically manufacture the chip.
    • Chip finishing which includes custom designations and structures to improve [oppoA3s[design for manufacturability (IC)|manufacturability]] of the layout. Examples of the latter are a seal ring and filler structures.[4]
    • Producing a reticle layout with test patterns and alignment marks.
    • Layout-to-mask preparation that enhances layout data with graphics operations, such as [oppoA3s[Resolution enhancement techniques]] or RET – methods for increasing the quality of the final [oppoA3s[photomask]]. This also includes [oppoA3s[Optical proximity correction]] or OPC – the up-front compensation for [oppoA3s[diffraction]] and [oppoA3s[Interference (wave propagation)|interference]] effects occurring later when chip is manufactured using this mask.
    • [oppoA3s[Mask generation]] – The generation of flat mask image from hierarchical design.
    • [oppoA3s[Automatic test pattern generation]] or ATPG – The generation of pattern data systematically to exercise as many logic-gates and other components as possible.
    • [oppoA3s[Built-in self-test]] or BIST – The installation of self-contained test-controllers to automatically test a logic or memory structure in the design

Functional safety

  • [oppoA3s[Functional safety analysis]], systematic computation of failure in time (FIT) rates and diagnostic coverage metrics for designs in order to meet the compliance requirements for the desired safety integrity levels.
  • [oppoA3s[Functional Safety Synthesis|Functional safety synthesis]], add reliability enhancements to structured elements (modules, RAMs, ROMs, register files, FIFOs) to improves fault detection / fault tolerance. These includes (not limited to), addition of error detection and / or correction codes (Hamming), redundant logic for fault detection and fault tolerance (duplicate / triplicate) and protocol checks (Interface parity, address alignment, beat count)
  • [oppoA3s[Functional Safety Verification|Functional safety verification]], running of a fault campaign, including insertion of faults into the design and verification that the safety mechanism reacts in an appropriate manner for the faults that are deemed covered.

[OppoA3s[Image:Gschem and gerbv.jpg|thumb|right|380px|PCB layout and schematic for connector design]]

Companies

{OppoA3s{Details|List of EDA companies}}

Old companies

[OppoA3s[Market capitalization]] and company name as of December 2011:[5]

  • $5.77 billion[6] – [oppoA3s[Synopsys]]
  • $4.46 billion[7] – [oppoA3s[Cadence Design Systems|Cadence]]
  • $2.33 billion – [oppoA3s[Mentor Graphics]]
  • $507 million – [oppoA3s[Magma Design Automation]]; Synopsys acquired Magma in February 2012[8][9]
  • NT$6.44 billion – SpringSoft; Synopsys acquired SpringSoft in August 2012
  • ¥11.95 billion – Zuken Inc.

Note: EEsof should likely be on this list,[10] but it does not have a market cap as it is the EDA division of Keysight.

Acquisitions

{OppoA3s{Main|List of EDA companies}} Many EDA companies acquire small companies with software or other technology that can be adapted to their core business.[11] Most of the market leaders are amalgamations of many smaller companies and this trend is helped by the tendency of software companies to design tools as accessories that fit naturally into a larger vendor's suite of programs on [oppoA3s[digital circuitry]]; many new tools incorporate analog design and mixed systems.[12] This is happening due to a trend to place [oppoA3s[System on a chip|entire electronic systems on a single chip]].

See also

{OppoA3s{Portal|Electronics}} {OppoA3s{Commons category}}

  • [OppoA3s[Computer-aided design]] (CAD)
  • [oppoA3s[Circuit design]]
  • [oppoA3s[EDA database]]
  • [oppoA3s[Signoff (electronic design automation)]]
  • [oppoA3s[Comparison of EDA software]]
  • [oppoA3s[Platform-based design]]

References

  1. ^ "About the EDA Industry". Electronic Design Automation Consortium. Archived from the original on August 2, 2015. Retrieved July 29, 2015.
  2. ^ J. Lienig, J. Scheible (2020). "Chap. 6: Special Layout Techniques for Analog IC Design". Fundamentals of Layout Design for Electronic Circuits. Springer. p. 213-256. ISBN 978-3-030-39284-0.
  3. ^ Lavagno, Martin, and Scheffer (2006). Electronic Design Automation For Integrated Circuits Handbook. Taylor and Francis. ISBN 0849330963.{{cite book}}: CS1 maint: multiple names: authors list (link)
  4. ^ {oppoA3s{Cite book|author=J. Lienig, J. Scheible|title=Fundamentals of Layout Design for Electronic Circuits|url=https://link.springer.com/book/10.1007/978-3-030-39284-0%7Cpage=102-110%7Cchapter=Chap. 3.3: Mask Data: Layout Post Processing|publisher=Springer|date=2020|doi=10.1007/978-3-030-39284-0|isbn=978-3-030-39284-0}}
  5. ^ Company Comparison - Google Finance. Google.com. Retrieved on 2013-08-10.
  6. ^ Synopsys, Inc.: NASDAQ:SNPS quotes & news - Google Finance. Google.com (2013-05-22). Retrieved on 2013-08-10.
  7. ^ CDNS Key Statistics | Cadence Design Systems, Inc. Stock - Yahoo! Finance. Finance.yahoo.com. Retrieved on 2013-08-10.
  8. ^ Dylan McGrath (30 Nov 2011). "Synopsys to buy Magma for $507 million". EETimes.
  9. ^ "Synopsys to Acquire Magma Design Automation".
  10. ^ "Agilent EEsof EDA – Part I".
  11. ^ Kirti Sikri Desai (2006). "EDA Innovation through Merger and Acquisitions". EDA Cafe. Retrieved March 23, 2010.
  12. ^ "Semi Wiki:EDA Mergers and Acquisitions Wiki". SemiWiki.com. 2011-01-16. Retrieved 2019-04-03.
Notes

{OppoA3s{Refbegin}}

  • http://www.staticfreesoft.com/documentsTextbook.html Computer Aids for VLSI Design by Steven M. Rubin
  • Fundamentals of Layout Design for Electronic Circuits, by Lienig, Scheible, Springer, {oppoA3s{doi|10.1007/978-3-030-39284-0}}{oppoA3s{ISBN|978-3-030-39284-0}}, 2020
  • VLSI Physical Design: From Graph Partitioning to Timing Closure, by Kahng, Lienig, Markov and Hu, {oppoA3s{doi|10.1007/978-90-481-9591-6}}{oppoA3s{ISBN|978-90-481-9590-9}}, 2011
  • Electronic Design Automation For Integrated Circuits Handbook, by Lavagno, Martin, and Scheffer, {oppoA3s{ISBN|0-8493-3096-3}}, 2006
  • The Electronic Design Automation Handbook, by Dirk Jansen et al., Kluwer Academic Publishers, {oppoA3s{ISBN|1-4020-7502-2}}, 2003, available also in German {oppoA3s{ISBN|3-446-21288-4}} (2005)
  • Combinatorial Algorithms for Integrated Circuit Layout, by Thomas Lengauer, {oppoA3s{ISBN|3-519-02110-2}}, Teubner Verlag, 1997.

{OppoA3s{Refend}} {OppoA3s{CAD software}} {OppoA3s{Computer science}} {OppoA3s{Authority control}}

{OppoA3s{DEFAULTSORT:Electronic Design Automation}} [OppoA3s[Category:Electronic design automation| ]] [OppoA3s[Category:Electronic engineering]]

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