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In [[digital logic]] design, '''quasi delay-insensitive (QDI)''' or ''speed independent (SI)'' circuits are the most robust class of [[asynchronous circuit]] that are still [[turing-complete]]. While [[delay-insensitive]] circuits make no assumptions regarding the delay of wires or gates and are not [[Turing-complete]]<ref name="martin1990" />, QDI circuits make the weakest delay assumption necessary to be so, the isochronic fork<ref name="manohar1995" />.
In [[digital logic]] design, '''quasi delay-insensitive (QDI)''' or ''speed independent (SI)'' circuits are the most robust class of [[asynchronous circuit]] that are still [[turing-complete]]. While [[delay-insensitive]] circuits make no assumptions regarding the delay of wires or gates and are not [[Turing-complete]]<ref group="timing" name="martin1990" />, QDI circuits make the weakest delay assumption necessary to be so, the isochronic fork<ref group="timing" name="manohar1995" />.


'''Pros'''
'''Pros'''
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Two cycles may interact using a [[c-element]] which waits for it's inputs to match before copying the value to it's output. This effectively forces the two cycles to synchronize at the [[c-element]]. Connecting three or more of these cycles in a line creates a [[Pipeline (computing)|pipeline]] allowing the cycles to trigger one after another like dominos.
Two cycles may interact using a [[c-element]] which waits for it's inputs to match before copying the value to it's output. This effectively forces the two cycles to synchronize at the [[c-element]]. Connecting three or more of these cycles in a line creates a [[Pipeline (computing)|pipeline]] allowing the cycles to trigger one after another like dominos.


This representation makes it relatively easy to understand small systems, but quickly becomes too much to manage as systems get larger. So, larger systems are partitioned into modules called ''processes'' which describe the interaction between a set of cycles. A ''process boundary'' cuts all of the participating cycles which then act as ''channel'' ports each with two [[Node (circuits)|circuit nodes]] called the ''request'' and ''acknowledge''. The process that drives the request is the ''sender'' while the process that drives the acknowledgement is the ''receiver''. Now, the sender and receiver communicate using certain [[communications protocol|protocols]]<ref name="tse2013" /> and the sequential triggering of communication actions from one process to the next is referred to as a ''token'' that traverses the pipeline.
This representation makes it relatively easy to understand small systems, but quickly becomes too much to manage as systems get larger. So, larger systems are partitioned into modules called ''processes'' which describe the interaction between a set of cycles. A ''process boundary'' cuts all of the participating cycles which then act as ''channel'' ports each with two [[Node (circuits)|circuit nodes]] called the ''request'' and ''acknowledge''. The process that drives the request is the ''sender'' while the process that drives the acknowledgement is the ''receiver''. Now, the sender and receiver communicate using certain [[communications protocol|protocols]]<ref group="synthesis" name="tse2013" /> and the sequential triggering of communication actions from one process to the next is referred to as a ''token'' that traverses the pipeline.


=== Stability and non-interference ===
=== Stability and non-interference ===


The correct operation of a QDI circuit requires that events be limited to [[Monotonic function|monotonic]] digital transitions. Instability ([[Hazard (logic)|glitch]]) or interference ([[Short circuit|short]]) can force the system into illegal states causing incorrect/unstable results, deadlock, and circuit damage. The previously described cyclic structure that ensures stability is called ''acknowledgement''. A transition <code>T1</code> is acknowledges another <code>T2</code> if there is a causal sequence of events from <code>T1</code> to <code>T2</code> that prevents <code>T2</code> from occurring until <code>T1</code> has completed<ref name="manohar2015" /><ref name="keller2009" /><ref name="martin1990" />. In a QDI circuit, every transition must acknowledge every one of the inputs to its associated gate. However, there are a few exceptions in which the stability property is guaranteed with timing assumptions rather than causality.
The correct operation of a QDI circuit requires that events be limited to [[Monotonic function|monotonic]] digital transitions. Instability ([[Hazard (logic)|glitch]]) or interference ([[Short circuit|short]]) can force the system into illegal states causing incorrect/unstable results, deadlock, and circuit damage. The previously described cyclic structure that ensures stability is called ''acknowledgement''. A transition <code>T1</code> is acknowledges another <code>T2</code> if there is a causal sequence of events from <code>T1</code> to <code>T2</code> that prevents <code>T2</code> from occurring until <code>T1</code> has completed<ref group="timing" name="manohar2015" /><ref group="timing" name="keller2009" /><ref group="timing" name="martin1990" />. In a QDI circuit, every transition must acknowledge every one of the inputs to its associated gate. However, there are a few exceptions in which the stability property is guaranteed with timing assumptions rather than causality.


==== Isochronic fork assumption ====
==== Isochronic fork assumption ====


An ''isochronic fork'' is a wire fork in which one end does not acknowledge the transition driving the wire. A good example of such a fork can be found in the standard implementation of a [[#PCHB|pre-charge half buffer]]. There are two types of Isochronic forks. An ''asymmetric isochronic fork'' assumes that the transition on the non-acknowledging end happens before or when the transition has been observed on the acknowledging end. A ''symmetric isochronic fork'' ensures that both ends observe the transition simultaneously. In QDI circuits, every transition that drives a wire fork must be acknowledged by at least one end of that fork. This concept was first introduced by A. J. Martin to distinguish between asynchronous circuits that satisfy QDI requirements and those that do not. Martin also established that it is impossible to design useful systems without including at least some isochronic forks given reasonable assumptions about the available circuit elements<ref name="martin1990" />. Isochronic forks were long thought to be the weakest compromise away from fully delay-insensitive systems.
An ''isochronic fork'' is a wire fork in which one end does not acknowledge the transition driving the wire. A good example of such a fork can be found in the standard implementation of a [[#PCHB|pre-charge half buffer]]. There are two types of Isochronic forks. An ''asymmetric isochronic fork'' assumes that the transition on the non-acknowledging end happens before or when the transition has been observed on the acknowledging end. A ''symmetric isochronic fork'' ensures that both ends observe the transition simultaneously. In QDI circuits, every transition that drives a wire fork must be acknowledged by at least one end of that fork. This concept was first introduced by A. J. Martin to distinguish between asynchronous circuits that satisfy QDI requirements and those that do not. Martin also established that it is impossible to design useful systems without including at least some isochronic forks given reasonable assumptions about the available circuit elements<ref group="timing" name="martin1990" />. Isochronic forks were long thought to be the weakest compromise away from fully delay-insensitive systems.


In fact, every CMOS gate has one or more internal isochronic forks between the pull-up and pull-down networks. The pull-down network only acknowledges the up-going transitions of the inputs while the pull-up network only acknowledges the down-going transitions.
In fact, every CMOS gate has one or more internal isochronic forks between the pull-up and pull-down networks. The pull-down network only acknowledges the up-going transitions of the inputs while the pull-up network only acknowledges the down-going transitions.
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==== Adversarial path assumption ====
==== Adversarial path assumption ====


The ''adversarial path assumption'' also deals with wire forks, but is ultimately weaker than the isochronic fork assumption. At some point in the circuit after a wire fork, the two paths must merge back into one. The ''adversarial path'' is the one that fails to acknowledge the transition on the wire fork. This assumption states that the transition propagating down the acknowledging path reaches the merge point after it would have down the adversarial path<ref name="keller2009" />. This effectively extends the isochronic fork assumption beyond the confines of the forked wire and into the connected paths of gates.
The ''adversarial path assumption'' also deals with wire forks, but is ultimately weaker than the isochronic fork assumption. At some point in the circuit after a wire fork, the two paths must merge back into one. The ''adversarial path'' is the one that fails to acknowledge the transition on the wire fork. This assumption states that the transition propagating down the acknowledging path reaches the merge point after it would have down the adversarial path<ref group="timing" name="keller2009" />. This effectively extends the isochronic fork assumption beyond the confines of the forked wire and into the connected paths of gates.


==== Half-cycle timing assumption ====
==== Half-cycle timing assumption ====


This assumption relaxes the QDI requirements a little further in the quest for performance. The [[c-element]] is effectively three gates, the logic, the driver, and the feedback and is non-inverting. This gets to be cumbersome and expensive if there is a need for a large amount of logic. The acknowledgement theorem states that the driver must acknowledge the logic. The ''half-cycle timing assumption'' assumes that the driver and feedback will stabilize before the inputs to the logic are allowed to switch<ref name="lafrieda2009" />. This allows the designer use the output of the logic directly, bypassing the driver and making shorter cycles for higher frequency processing.
This assumption relaxes the QDI requirements a little further in the quest for performance. The [[c-element]] is effectively three gates, the logic, the driver, and the feedback and is non-inverting. This gets to be cumbersome and expensive if there is a need for a large amount of logic. The acknowledgement theorem states that the driver must acknowledge the logic. The ''half-cycle timing assumption'' assumes that the driver and feedback will stabilize before the inputs to the logic are allowed to switch<ref group="timing" name="lafrieda2009" />. This allows the designer use the output of the logic directly, bypassing the driver and making shorter cycles for higher frequency processing.


==== Atomic complex gates ====
==== Atomic complex gates ====


A large amount of the automatic synthesis literature uses ''atomic complex gates''. A tree of gates is assumed to transition completely before any of the inputs at the leaves of the tree are allowed to switch again<ref name="meng1989" /><ref name="cortadella1998" />. While this assumption allows automatic synthesis tools to bypass the bubble reshuffling problem, the reliability of these gates tends to be difficult to guarantee.
A large amount of the automatic synthesis literature uses ''atomic complex gates''. A tree of gates is assumed to transition completely before any of the inputs at the leaves of the tree are allowed to switch again<ref group="timing" name="meng1989" /><ref group="timing" name="cortadella1998" />. While this assumption allows automatic synthesis tools to bypass the bubble reshuffling problem, the reliability of these gates tends to be difficult to guarantee.


==== Relative timing ====
==== Relative timing ====


''Relative Timing'' is a framework for making and implementing arbitrary timing assumptions in QDI circuits. It represents a timing assumption as a virtual causality arc to complete a broken cycle in the event graph. This allows designers to reason about timing assumptions as a method to realize circuits with higher throughput and energy efficiency by systematically sacrificing robustness <ref name="stevens2003" /><ref name="manoranjan2016" />.
''Relative Timing'' is a framework for making and implementing arbitrary timing assumptions in QDI circuits. It represents a timing assumption as a virtual causality arc to complete a broken cycle in the event graph. This allows designers to reason about timing assumptions as a method to realize circuits with higher throughput and energy efficiency by systematically sacrificing robustness <ref group="timing" name="stevens2003" /><ref group="timing" name="manoranjan2016" />.


== Representations ==
== Representations ==
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=== Communicating hardware processes (CHP) ===
=== Communicating hardware processes (CHP) ===


''Communicating hardware processes (CHP)'' is a program notation for QDI circuits inspired by [[Tony Hoare]]'s [[Communicating sequential processes|communicating sequential processes (CSP)]]<ref name="hoare1978" /> and [[Edsger W. Dijkstra]]'s [[Guarded Command Language|guarded commands]]<ref name="dijkstra1975" />. The syntax is described below in descending precedence.<ref name="martin1991" />
''Communicating hardware processes (CHP)'' is a program notation for QDI circuits inspired by [[Tony Hoare]]'s [[Communicating sequential processes|communicating sequential processes (CSP)]] and [[Edsger W. Dijkstra]]'s [[Guarded Command Language|guarded commands]]. The syntax is described below in descending precedence.<ref group="synthesis" name="martin1991" />


* '''Skip''' <code>skip</code> does nothing. It simply acts as a placeholder for pass-through conditions.
* '''Skip''' <code>skip</code> does nothing. It simply acts as a placeholder for pass-through conditions.
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==== Event-rule systems (ER) ====
==== Event-rule systems (ER) ====
''Event-rule systems (ER)'' use a similar notation to implement a restricted subset of petri net functionality in which there are transitions and arcs, but no places. This means that the baseline ER system lacks choice as implemented by conditional splits and merges in a petri net and disjunction implemented by conditional merges. The baseline ER system also doesn't allow feedback, So, it effectively represents a trace of the transitions that fired during the execution of a QDI circuit and is typically used to for timing and sizing optimizations<ref name="burns1991" />.
''Event-rule systems (ER)'' use a similar notation to implement a restricted subset of petri net functionality in which there are transitions and arcs, but no places. This means that the baseline ER system lacks choice as implemented by conditional splits and merges in a petri net and disjunction implemented by conditional merges. The baseline ER system also doesn't allow feedback, So, it effectively represents a trace of the transitions that fired during the execution of a QDI circuit and is typically used to for timing and sizing optimizations<ref group="sizing" name="burns1991" />.
''Repetitive event-rule systems (RER)'' add feedback by folding the trace back on itself, marking the fold point with a tick mark<ref name="burns1991" />. ''Extended event-rule systems (XER)'' add disjunction<ref name="lee1995" />.
''Repetitive event-rule systems (RER)'' add feedback by folding the trace back on itself, marking the fold point with a tick mark<ref group="sizing" name="burns1991" />. ''Extended event-rule systems (XER)'' add disjunction<ref group="sizing" name="lee1995" />.


=== Production rule set (PRS) ===
=== Production rule set (PRS) ===
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== References ==
== References ==
⚫
=== Synthesis ===
⚫
{{Reflist|refs=
{{Reflist|group=synthesis|refs=
⚫
<ref name="martin1990">{{cite journal | author=Martin, Alain J. | title=The Limitations to Delay-Insensitivity in Asynchronous Circuits | journal=Sixth MIT Conference on Advanced Research in VLSI | publisher=MIT Press | year=1990 | url=http://authors.library.caltech.edu/26721/2/postscript.pdf}}</ref>
⚫
<ref name="martin1991">{{cite thesis|last=Martin|first=Alain|date=1991|title=Synthesis of Asynchronous VLSI Circuits|type=Ph.D.|publisher=California Institute of Technology|url=https://authors.library.caltech.edu/26746/2/postscript.pdf}}</ref>
⚫
<ref name="manohar1999">{{cite journal|last1=Manohar|first1=Rajit|last2=Lee|first2=Tak-Kwan|last3=Martin|first3=Alain|title=Projection: a synthesis technique for concurrent systems|journal=Advanced Research in Asynchronous Circuits and Systems|date=1999|doi=10.1109/ASYNC.1999.761528|url=http://vlsi.cornell.edu/~rajit/ps/proj.pdf}}</ref>
<ref name="manohar2001">{{Cite journal|last=Manohar|first=R.|date=2001|title=An analysis of reshuffled handshaking expansions|url=https://pdfs.semanticscholar.org/54ea/8135c3b572f6afa97b1718699a0e1981b736.pdf|journal=Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001|pages=96–105|doi=10.1109/async.2001.914073}}</ref>
⚫
<ref name="lines1998">{{Cite journal|last=Lines|first=Andrew|date=1998|title=Pipelined Asynchronous Circuits|type=Ph.D.|publisher=California Institute of Technology|url=https://authors.library.caltech.edu/26834/5/CSTR1998.pdf|doi=10.7907/z92v2d4z}}</ref>
<ref name="manohar1998">{{Cite journal|last=Manohar|first=Rajit|last2=Martin|first2=Alain J.|date=1998-06-15|title=Slack elasticity in concurrent computing|url=http://vlsi.cornell.edu/~rajit/ps/mpc98.pdf|journal=Mathematics of Program Construction|series=Lecture Notes in Computer Science|language=en|publisher=Springer, Berlin, Heidelberg|pages=272–285|doi=10.1007/bfb0054295|isbn=9783540645917}}</ref>
⚫
<ref name="tse2013">{{cite journal|first1=Jonathan|last1=Tse|first2=Benjamin|last2=Hill|first3=Rajit|last3=Manohar|title=A Bit of Analysis on Self-Timed Single-Bit On-Chip Links|publisher=Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)|date=May 2013|url=http://csl.yale.edu/~rajit/ps/bitlinks.pdf|doi=10.1109/ASYNC.2013.26}}</ref>
}}
=== Timing ===
{{Reflist|group=timing|refs=
<ref name="manohar1995">{{cite journal|last1=Manohar|first1=Rajit|last2=Martin|first2=Alain|title=Quasi-Delay-Insensitive Circuits are Turing-Complete|url=http://vlsi.cornell.edu/~rajit/ps/qdi.pdf|doi=10.7907/Z9H70CV1|date=1995|publisher=California Institute of Technology}}</ref>
<ref name="manohar1995">{{cite journal|last1=Manohar|first1=Rajit|last2=Martin|first2=Alain|title=Quasi-Delay-Insensitive Circuits are Turing-Complete|url=http://vlsi.cornell.edu/~rajit/ps/qdi.pdf|doi=10.7907/Z9H70CV1|date=1995|publisher=California Institute of Technology}}</ref>
⚫
<ref name="martin1990">{{cite journal | author=Martin, Alain J. | title=The Limitations to Delay-Insensitivity in Asynchronous Circuits | journal=Sixth MIT Conference on Advanced Research in VLSI | publisher=MIT Press | year=1990 | url=http://authors.library.caltech.edu/26721/2/postscript.pdf}}</ref>
<ref name="manohar2015">{{Cite journal|last=Manohar|first=R.|last2=Moses|first2=Y.|date=May 2015|title=Analyzing Isochronic Forks with Potential Causality|url=http://vlsi.cornell.edu/~rajit/ps/isoforks.pdf|journal=2015 21st IEEE International Symposium on Asynchronous Circuits and Systems|pages=69–76|doi=10.1109/async.2015.19}}</ref>
<ref name="manohar2015">{{Cite journal|last=Manohar|first=R.|last2=Moses|first2=Y.|date=May 2015|title=Analyzing Isochronic Forks with Potential Causality|url=http://vlsi.cornell.edu/~rajit/ps/isoforks.pdf|journal=2015 21st IEEE International Symposium on Asynchronous Circuits and Systems|pages=69–76|doi=10.1109/async.2015.19}}</ref>
<ref name="keller2009">{{Cite journal|last=Keller|first=S.|last2=Katelman|first2=M.|last3=Martin|first3=A. J.|date=May 2009|title=A Necessary and Sufficient Timing Assumption for Speed-Independent Circuits|url=http://authors.library.caltech.edu/18164/1/Keller2009p8391Async_2009_15Th_Ieee_International_Symposium_On_Asynchronous_Circuits_And_Systems.pdf|journal=2009 15th IEEE Symposium on Asynchronous Circuits and Systems|pages=65–76|doi=10.1109/async.2009.27}}</ref>
<ref name="keller2009">{{Cite journal|last=Keller|first=S.|last2=Katelman|first2=M.|last3=Martin|first3=A. J.|date=May 2009|title=A Necessary and Sufficient Timing Assumption for Speed-Independent Circuits|url=http://authors.library.caltech.edu/18164/1/Keller2009p8391Async_2009_15Th_Ieee_International_Symposium_On_Asynchronous_Circuits_And_Systems.pdf|journal=2009 15th IEEE Symposium on Asynchronous Circuits and Systems|pages=65–76|doi=10.1109/async.2009.27}}</ref>
<ref name="lafrieda2009">{{Cite journal|last=LaFrieda|first=C.|last2=Manohar|first2=R.|date=May 2009|title=Reducing Power Consumption with Relaxed Quasi Delay-Insensitive Circuits|url=http://csl.yale.edu/~rajit/ps/rqdi.pdf|journal=2009 15th IEEE Symposium on Asynchronous Circuits and Systems|pages=217–226|doi=10.1109/async.2009.9}}</ref>
<ref name="lafrieda2009">{{Cite journal|last=LaFrieda|first=C.|last2=Manohar|first2=R.|date=May 2009|title=Reducing Power Consumption with Relaxed Quasi Delay-Insensitive Circuits|url=http://csl.yale.edu/~rajit/ps/rqdi.pdf|journal=2009 15th IEEE Symposium on Asynchronous Circuits and Systems|pages=217–226|doi=10.1109/async.2009.9}}</ref>
⚫
<ref name="tse2013">{{cite journal|first1=Jonathan|last1=Tse|first2=Benjamin|last2=Hill|first3=Rajit|last3=Manohar|title=A Bit of Analysis on Self-Timed Single-Bit On-Chip Links|publisher=Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)|date=May 2013|url=http://csl.yale.edu/~rajit/ps/bitlinks.pdf|doi=10.1109/ASYNC.2013.26}}</ref>
<ref name="cortadella1998">{{Cite journal|last=Pastor|first=E.|last2=Cortadella|first2=J.|last3=Kondratyev|first3=A.|last4=Roig|first4=O.|date=November 1998|title=Structural methods for the synthesis of speed-independent circuits|url=http://www.cs.upc.edu/~jordicf/gavina/BIB/files/tcad98_struct.pdf|journal=IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|volume=17|issue=11|pages=1108–1129|doi=10.1109/43.736185|issn=0278-0070}}</ref>
<ref name="cortadella1998">{{Cite journal|last=Pastor|first=E.|last2=Cortadella|first2=J.|last3=Kondratyev|first3=A.|last4=Roig|first4=O.|date=November 1998|title=Structural methods for the synthesis of speed-independent circuits|url=http://www.cs.upc.edu/~jordicf/gavina/BIB/files/tcad98_struct.pdf|journal=IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|volume=17|issue=11|pages=1108–1129|doi=10.1109/43.736185|issn=0278-0070}}</ref>
<ref name="meng1989">{{Cite journal|last=Meng|first=T. H. Y.|last2=Brodersen|first2=R. W.|last3=Messerschmitt|first3=D. G.|date=November 1989|title=Automatic synthesis of asynchronous circuits from high-level specifications|url=http://ieeexplore.ieee.org/document/41504/|journal=IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|volume=8|issue=11|pages=1185–1205|doi=10.1109/43.41504|issn=0278-0070}}</ref>
<ref name="meng1989">{{Cite journal|last=Meng|first=T. H. Y.|last2=Brodersen|first2=R. W.|last3=Messerschmitt|first3=D. G.|date=November 1989|title=Automatic synthesis of asynchronous circuits from high-level specifications|url=http://ieeexplore.ieee.org/document/41504/|journal=IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|volume=8|issue=11|pages=1185–1205|doi=10.1109/43.41504|issn=0278-0070}}</ref>
<ref name="stevens2003">{{Cite journal|last=Stevens|first=K. S.|last2=Ginosar|first2=R.|last3=Rotem|first3=S.|date=February 2003|title=Relative timing [asynchronous design]|url=http://webee.technion.ac.il/~ran/papers/TVLSI-RelativeTiming-2002.pdf|journal=IEEE Transactions on Very Large Scale Integration (VLSI) Systems|volume=11|issue=1|pages=129–140|doi=10.1109/tvlsi.2002.801606|issn=1063-8210}}</ref>
<ref name="stevens2003">{{Cite journal|last=Stevens|first=K. S.|last2=Ginosar|first2=R.|last3=Rotem|first3=S.|date=February 2003|title=Relative timing|url=http://webee.technion.ac.il/~ran/papers/TVLSI-RelativeTiming-2002.pdf|journal=IEEE Transactions on Very Large Scale Integration (VLSI) Systems|volume=11|issue=1|pages=129–140|doi=10.1109/tvlsi.2002.801606|issn=1063-8210}}</ref>
<ref name="manoranjan2016">{{Cite journal|last=Manoranjan|first=J. V.|last2=Stevens|first2=K. S.|date=May 2016|title=Qualifying Relative Timing Constraints for Asynchronous Circuits|url=http://www.ece.utah.edu/~kstevens/docs/async16.pdf|journal=2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)|pages=91–98|doi=10.1109/async.2016.23}}</ref>
<ref name="manoranjan2016">{{Cite journal|last=Manoranjan|first=J. V.|last2=Stevens|first2=K. S.|date=May 2016|title=Qualifying Relative Timing Constraints for Asynchronous Circuits|url=http://www.ece.utah.edu/~kstevens/docs/async16.pdf|journal=2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)|pages=91–98|doi=10.1109/async.2016.23}}</ref>
}}

=== Verification ===
<ref name="hoare1978">{{Cite journal|last=Hoare|first=C. A. R.|date=August 1978|title=Communicating Sequential Processes|url=http://usingcsp.com/cspbook.pdf|journal=Commun. ACM|volume=21|issue=8|pages=666–677|doi=10.1145/359576.359585|issn=0001-0782}}</ref>
{{Reflist|group=verification|refs=
<ref name="dijkstra1975">{{Cite journal|last=Dijkstra|first=Edsger W.|date=August 1975|title=Guarded Commands, Nondeterminacy and Formal Derivation of Programs|url=https://www.cs.virginia.edu/~weimer/2008-615/reading/DijkstraGC.pdf|journal=Commun. ACM|volume=18|issue=8|pages=453–457|doi=10.1145/360933.360975|issn=0001-0782}}</ref>
⚫
<ref name="longfield2013">{{Cite journal|last=Longfield|first=S. J.|last2=Manohar|first2=R.|date=May 2013|title=Inverting Martin Synthesis for Verification|url=http://csl.yale.edu/~rajit/ps/invsynth.pdf|journal=2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems|pages=150–157|doi=10.1109/async.2013.10}}</ref>
⚫
<ref name="martin1991">{{cite thesis|last=Martin|first=Alain|date=1991|title=Synthesis of Asynchronous VLSI Circuits|type=Ph.D.|publisher=California Institute of Technology|url=https://authors.library.caltech.edu/26746/2/postscript.pdf}}</ref>
⚫
<ref name="longfield2015">{{Cite journal|last=Longfield|first=Stephen|last2=Nkounkou|first2=Brittany|last3=Manohar|first3=Rajit|last4=Tate|first4=Ross|date=2015|title=Preventing Glitches and Short Circuits in High-level Self-timed Chip Specifications|url=http://vlsi.cornell.edu/~rajit/ps/chpeffects_pldi.pdf|journal=Proceedings of the 36th ACM SIGPLAN Conference on Programming Language Design and Implementation|series=PLDI '15|location=New York, NY, USA|publisher=ACM|pages=270–279|doi=10.1145/2737924.2737967|isbn=9781450334686}}</ref>

}}
=== Sizing ===
{{Reflist|group=sizing|refs=
<ref name="burns1991">{{cite thesis|last=Burns|first=Steven|date=1991|title=Performance Analysis and Optimization of Asynchronous Circuits|type=Ph.D.|publisher=California Institute of Technology|url=http://resolver.caltech.edu/CaltechCSTR:1991.cs-tr-91-01}}</ref>
<ref name="burns1991">{{cite thesis|last=Burns|first=Steven|date=1991|title=Performance Analysis and Optimization of Asynchronous Circuits|type=Ph.D.|publisher=California Institute of Technology|url=http://resolver.caltech.edu/CaltechCSTR:1991.cs-tr-91-01}}</ref>
<ref name="lee1995">{{cite thesis|last=Lee|first=Tak-Kwan|date=1995|title=A General Approach to Performance Analysis and Optimization of Asynchronous Circuits|type=Ph.D.|publisher=Defense Technical Information Center|url=http://www.dtic.mil/docs/citations/ADA444282}}</ref>
<ref name="lee1995">{{cite thesis|last=Lee|first=Tak-Kwan|date=1995|title=A General Approach to Performance Analysis and Optimization of Asynchronous Circuits|type=Ph.D.|publisher=Defense Technical Information Center|url=http://www.dtic.mil/docs/citations/ADA444282}}</ref>
}}
}}

== Further reading ==

⚫
=== Synthesis ===

⚫
* {{cite journal|last1=Manohar|first1=Rajit|last2=Lee|first2=Tak-Kwan|last3=Martin|first3=Alain|title=Projection: a synthesis technique for concurrent systems|journal=Advanced Research in Asynchronous Circuits and Systems|date=1999|doi=10.1109/ASYNC.1999.761528|url=http://ieeexplore.ieee.org/abstract/document/761528/}}
* {{cite thesis|last=Martin|first=Alain|date=1991|title=Synthesis of Asynchronous VLSI Circuits|type=Ph.D.|publisher=California Institute of Technology|url=http://resolver.caltech.edu/CaltechCSTR:1991.cs-tr-93-28}}
⚫
* {{cite thesis|last=Lines|first=Andrew|date=1998 |title=Pipelined Asynchronous Circuits|type=Ph.D.|publisher=California Institute of Technology|url=http://resolver.caltech.edu/CaltechCSTR:1998.cs-tr-95-21}}
⚫
* {{cite journal|last1=Martin|first1=Alain|last2=Burns|first2=Steven|last3=Lee|first3=Tak-Kwan|title=The design of an asynchronous microprocessor|date=1989|doi=10.1145/71317.1186643|url=http://resolver.caltech.edu/CaltechAUTHORS:20161130-144153368}}

=== Formal verification ===

⚫
* {{Cite journal|last=Longfield|first=S. J.|last2=Manohar|first2=R.|date=May 2013|title=Inverting Martin Synthesis for Verification|url=http://csl.yale.edu/~rajit/ps/invsynth.pdf|journal=2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems|pages=150–157|doi=10.1109/async.2013.10}}
⚫
* {{Cite journal|last=Longfield|first=Stephen|last2=Nkounkou|first2=Brittany|last3=Manohar|first3=Rajit|last4=Tate|first4=Ross|date=2015|title=Preventing Glitches and Short Circuits in High-level Self-timed Chip Specifications|url=http://vlsi.cornell.edu/~rajit/ps/chpeffects_pldi.pdf|journal=Proceedings of the 36th ACM SIGPLAN Conference on Programming Language Design and Implementation|series=PLDI '15|location=New York, NY, USA|publisher=ACM|pages=270–279|doi=10.1145/2737924.2737967|isbn=9781450334686}}

=== Timing analysis and optimization ===

* {{cite thesis|last=Burns|first=Steven|date=1991|title=Performance Analysis and Optimization of Asynchronous Circuits|type=Ph.D.|publisher=California Institute of Technology|url=http://resolver.caltech.edu/CaltechCSTR:1991.cs-tr-91-01}}
* {{cite thesis|last=Lee|first=Tak-Kwan|date=1995|title=A General Approach to Performance Analysis and Optimization of Asynchronous Circuits|type=Ph.D.|publisher=Defense Technical Information Center|url=http://www.dtic.mil/docs/citations/ADA444282}}

=== Layout ===
=== Layout ===
{{Reflist|group=layout|refs=

* {{Cite journal|last=Karmazin|first=R.|last2=Longfield|first2=S.|last3=Otero|first3=C. T. O.|last4=Manohar|first4=R.|date=May 2015|title=Timing Driven Placement for Quasi Delay-Insensitive Circuits|url=http://csl.yale.edu/~rajit/ps/tdplacement.pdf|journal=2015 21st IEEE International Symposium on Asynchronous Circuits and Systems|pages=45–52|doi=10.1109/async.2015.16}}
<ref name="karmazin2015">{{Cite journal|last=Karmazin|first=R.|last2=Longfield|first2=S.|last3=Otero|first3=C. T. O.|last4=Manohar|first4=R.|date=May 2015|title=Timing Driven Placement for Quasi Delay-Insensitive Circuits|url=http://csl.yale.edu/~rajit/ps/tdplacement.pdf|journal=2015 21st IEEE International Symposium on Asynchronous Circuits and Systems|pages=45–52|doi=10.1109/async.2015.16}}</ref>
}}

=== Chips ===
⚫
{{Reflist|group=chips|refs=
⚫
<ref name="martin1989">{{cite journal|last1=Martin|first1=Alain|last2=Burns|first2=Steven|last3=Lee|first3=Tak-Kwan|title=The design of an asynchronous microprocessor|date=1989|doi=10.1145/71317.1186643|url=http://resolver.caltech.edu/CaltechAUTHORS:20161130-144153368}}</ref>
<ref name="nanya1994>{{Cite journal|last=Nanya|first=T.|last2=Ueno|first2=Y.|last3=Kagotani|first3=H.|last4=Kuwako|first4=M.|last5=Takamura|first5=A.|date=Summer 1994|title=TITAC: design of a quasi-delay-insensitive microprocessor|url=http://www.ee.bgu.ac.il/~kushnero/asynchronous/TITAC%20quasi-delay-insensitive%20microprocessor.pdf|journal=IEEE Design Test of Computers|volume=11|issue=2|pages=50–63|doi=10.1109/54.282445|issn=0740-7475}}</ref>
<ref name=takamura1997>{{Cite journal|last=Takamura|first=A.|last2=Kuwako|first2=M.|last3=Imai|first3=M.|last4=Fujii|first4=T.|last5=Ozawa|first5=M.|last6=Fukasaku|first6=I.|last7=Ueno|first7=Y.|last8=Nanya|first8=T.|date=October 1997|title=TITAC-2: an asynchronous 32-bit microprocessor based on scalable-delay-insensitive model|url=https://pdfs.semanticscholar.org/181e/7bf4f9c81cffb5ac85ab7b098c26e6b68b35.pdf|journal=Proceedings International Conference on Computer Design VLSI in Computers and Processors|pages=288–294|doi=10.1109/iccd.1997.628881}}</ref>
}}
=== Tools ===
=== Tools ===

* {{cite web|title=Petrify: a tool for synthesis of Petri Nets and asynchronous circuits|url=http://www.cs.upc.edu/~jordicf/petrify/|website=UPC/DAC VLSI CAD Group|accessdate=6 October 2017}}
* {{cite web|title=Petrify: a tool for synthesis of Petri Nets and asynchronous circuits|url=http://www.cs.upc.edu/~jordicf/petrify/|website=UPC/DAC VLSI CAD Group|accessdate=6 October 2017}}
* {{cite web|last=Fang|first=David|title=The Hierarchical Asynchronous Circuit Kompiler Toolkit|url=http://vlsi.cornell.edu/~fang/hackt/|accessdate=6 October 2017}}
* {{cite web|last=Fang|first=David|title=The Hierarchical Asynchronous Circuit Kompiler Toolkit|url=http://vlsi.cornell.edu/~fang/hackt/|accessdate=6 October 2017}}
* {{cite web|title=Balsa Asynchronous Synthesis System|url=https://github.com/kristofferkoch/Balsa|accessdate=6 October 2017}}
* {{cite web|title=Balsa Asynchronous Synthesis System|url=https://github.com/kristofferkoch/Balsa|accessdate=6 October 2017}}

=== Tutorials ===
=== Tutorials ===

* {{cite web|title=Introduction to Asynchronous Circuits|url=https://docs.google.com/presentation/d/11w59jPf3YmbpAyRkBiP9-37KjHjU1f4FMW0M1xEFANQ/edit?usp=sharing}}
* {{cite web|title=Introduction to Asynchronous Circuits|url=https://docs.google.com/presentation/d/11w59jPf3YmbpAyRkBiP9-37KjHjU1f4FMW0M1xEFANQ/edit?usp=sharing}}
* {{cite web|title=Weak Condition Half Buffer|url=https://docs.google.com/presentation/d/1rhX8NpYjSPOusMYqh9mkT4VHOUP-ZH7LzGWJoKh6vrs/edit?usp=sharing}}
* {{cite web|title=Weak Condition Half Buffer|url=https://docs.google.com/presentation/d/1rhX8NpYjSPOusMYqh9mkT4VHOUP-ZH7LzGWJoKh6vrs/edit?usp=sharing}}

Revision as of 13:19, 14 October 2017

In digital logic design, quasi delay-insensitive (QDI) or speed independent (SI) circuits are the most robust class of asynchronous circuit that are still turing-complete. While delay-insensitive circuits make no assumptions regarding the delay of wires or gates and are not Turing-complete[timing 1], QDI circuits make the weakest delay assumption necessary to be so, the isochronic fork[timing 2].

Pros

  • QDI circuits will operate correctly regardless of timing variations produced by process variation, temperature fluctuation, circuit redesign, and FPGA remapping as long as the isochronic fork assumption is not violated.
  • Control circuitry requiring complex event sequencing comes naturally in QDI circuits.
  • Idle devices do not switch and QDI processes have a cycle time dependent upon the computation. This gives designers the opportunity to save dynamic power and increase throughput by optimizing for average-case workload characteristics instead of worst-case.

Cons

  • Data encoding is extremely sparse, typically requiring twice as many wires.
  • QDI circuits require many more devices than synchronous circuits to implement the same functionality.
  • The baseline QDI pipeline is slower and more power hungry than the baseline synchronous pipeline.

Theory

QDI pipeline circuit
QDI pipeline event rule system

A QDI circuit is a system of events which are organized as a network of interacting cycles. In this system, a gate is mapped to two events in which it's output node is driven either from GND to Vdd by the pull up network or from Vdd to GND by the pull down network. Furthermore, these two events must belong to the same cycles and every cycle must have an odd number of gates. The simplest example, a ring oscillator, consists of exactly one cycle of three gates (six events).

Two cycles may interact using a c-element which waits for it's inputs to match before copying the value to it's output. This effectively forces the two cycles to synchronize at the c-element. Connecting three or more of these cycles in a line creates a pipeline allowing the cycles to trigger one after another like dominos.

This representation makes it relatively easy to understand small systems, but quickly becomes too much to manage as systems get larger. So, larger systems are partitioned into modules called processes which describe the interaction between a set of cycles. A process boundary cuts all of the participating cycles which then act as channel ports each with two circuit nodes called the request and acknowledge. The process that drives the request is the sender while the process that drives the acknowledgement is the receiver. Now, the sender and receiver communicate using certain protocols[synthesis 1] and the sequential triggering of communication actions from one process to the next is referred to as a token that traverses the pipeline.

Stability and non-interference

The correct operation of a QDI circuit requires that events be limited to monotonic digital transitions. Instability (glitch) or interference (short) can force the system into illegal states causing incorrect/unstable results, deadlock, and circuit damage. The previously described cyclic structure that ensures stability is called acknowledgement. A transition T1 is acknowledges another T2 if there is a causal sequence of events from T1 to T2 that prevents T2 from occurring until T1 has completed[timing 3][timing 4][timing 1]. In a QDI circuit, every transition must acknowledge every one of the inputs to its associated gate. However, there are a few exceptions in which the stability property is guaranteed with timing assumptions rather than causality.

Isochronic fork assumption

An isochronic fork is a wire fork in which one end does not acknowledge the transition driving the wire. A good example of such a fork can be found in the standard implementation of a pre-charge half buffer. There are two types of Isochronic forks. An asymmetric isochronic fork assumes that the transition on the non-acknowledging end happens before or when the transition has been observed on the acknowledging end. A symmetric isochronic fork ensures that both ends observe the transition simultaneously. In QDI circuits, every transition that drives a wire fork must be acknowledged by at least one end of that fork. This concept was first introduced by A. J. Martin to distinguish between asynchronous circuits that satisfy QDI requirements and those that do not. Martin also established that it is impossible to design useful systems without including at least some isochronic forks given reasonable assumptions about the available circuit elements[timing 1]. Isochronic forks were long thought to be the weakest compromise away from fully delay-insensitive systems.

In fact, every CMOS gate has one or more internal isochronic forks between the pull-up and pull-down networks. The pull-down network only acknowledges the up-going transitions of the inputs while the pull-up network only acknowledges the down-going transitions.

Adversarial path assumption

The adversarial path assumption also deals with wire forks, but is ultimately weaker than the isochronic fork assumption. At some point in the circuit after a wire fork, the two paths must merge back into one. The adversarial path is the one that fails to acknowledge the transition on the wire fork. This assumption states that the transition propagating down the acknowledging path reaches the merge point after it would have down the adversarial path[timing 4]. This effectively extends the isochronic fork assumption beyond the confines of the forked wire and into the connected paths of gates.

Half-cycle timing assumption

This assumption relaxes the QDI requirements a little further in the quest for performance. The c-element is effectively three gates, the logic, the driver, and the feedback and is non-inverting. This gets to be cumbersome and expensive if there is a need for a large amount of logic. The acknowledgement theorem states that the driver must acknowledge the logic. The half-cycle timing assumption assumes that the driver and feedback will stabilize before the inputs to the logic are allowed to switch[timing 5]. This allows the designer use the output of the logic directly, bypassing the driver and making shorter cycles for higher frequency processing.

Atomic complex gates

A large amount of the automatic synthesis literature uses atomic complex gates. A tree of gates is assumed to transition completely before any of the inputs at the leaves of the tree are allowed to switch again[timing 6][timing 7]. While this assumption allows automatic synthesis tools to bypass the bubble reshuffling problem, the reliability of these gates tends to be difficult to guarantee.

Relative timing

Relative Timing is a framework for making and implementing arbitrary timing assumptions in QDI circuits. It represents a timing assumption as a virtual causality arc to complete a broken cycle in the event graph. This allows designers to reason about timing assumptions as a method to realize circuits with higher throughput and energy efficiency by systematically sacrificing robustness [timing 8][timing 9].

Representations

Communicating hardware processes (CHP)

Communicating hardware processes (CHP) is a program notation for QDI circuits inspired by Tony Hoare's communicating sequential processes (CSP) and Edsger W. Dijkstra's guarded commands. The syntax is described below in descending precedence.[synthesis 2]

  • Skip skip does nothing. It simply acts as a placeholder for pass-through conditions.
  • Dataless assignment a+ sets the voltage of the node x to Vdd while a- sets the voltage of the node to GND.
  • Assignment a := e evaluates the expression e then assigns the resulting value to the variable x.
  • Send X!e evaluates the expression e then sends the resulting value across the channel X. X! is a dataless send.
  • Receive X?a waits until there is a valid value on the channel X then assigns that value to the variable a. X? is a dataless receive.
  • Probe #X returns the value waiting on the channel X without executing the receive.
  • Simultaneous composition S * T executes the process fragments S and T at the same time.
  • Internal parallel composition S, T executes the process fragments S and T in any order.
  • Sequential composition S; T executes the process fragments S followed by T.
  • Parallel composition S || T executes the process fragments S and T in any order. This is functionally equivalent to internal parallel composition but with lower precedence.
  • Deterministic selection [G0 -> S0[]G1 -> S1[]...[]Gn -> Sn] implements choice in which G0,G1,...,Gn are guards which are dataless boolean expressions or data expressions that are implicitly cast using a validity check and S0,S1,...,Sn are process fragments. Deterministic selection waits until one of the guards evaluates to Vdd, then proceeds to execute the guard's associated process fragment. If two guards evaluate to Vdd during the same window of time, an error occurs. [G] is shorthand for [G -> skip] and simply implements a wait.
  • Non-deterministic selection [G0 -> S0:G1 -> S1:...:Gn -> Sn] is the same as deterministic selection except that more than one guard is allowed to evaluate to Vdd. Only the process fragment associated with the first guard to evaluate to Vdd is executed.
  • Repetition *[G0 -> S0[]G1 -> S1[]...[]Gn -> Sn] or *[G0 -> S0:G1 -> S1:...:Gn -> Sn] is similar to the associated selection statements except that the action is repeated while any guard evaluates to Vdd. *[S] is shorthand for *[Vdd -> S] and implements infinite repetition.

Hand-shaking expansions (HSE)

Hand-shaking expansions are a subset of CHP in which only dataless operators are permitted. This is an intermediate representation toward the synthesis of QDI circuits.

Petri nets (PN)

Main article: Petri net

A petri net (PN) is a bipartite graph of places and transitions used as a model for QDI circuits. Transitions in the petri net represent voltage transitions on nodes in the circuit. Places represent the partial states between transitions. A token inside a place acts as a program counter identifying the current state of the system and multiple tokens may exist in a petri net simultaneously. However, for QDI circuits multiple tokens in the same place is an error.

When a transition has tokens on every input place, that transition is enabled. When the transition fires, the tokens are removed from the input places and new tokens are created on all of the output places. This means that a transition that has multiple output places is a parallel split and a transition with multiple input places is a parallel merge. If a place has multiple output transitions, then any one of those transitions could fire. However, doing so would remove the token from the place and prevent any other transition from firing. This effectively implements choice. Therefore, a place with multiple output transitions is a conditional split and a place with multiple input transitions is a conditional merge.

Event-rule systems (ER)

Event-rule systems (ER) use a similar notation to implement a restricted subset of petri net functionality in which there are transitions and arcs, but no places. This means that the baseline ER system lacks choice as implemented by conditional splits and merges in a petri net and disjunction implemented by conditional merges. The baseline ER system also doesn't allow feedback, So, it effectively represents a trace of the transitions that fired during the execution of a QDI circuit and is typically used to for timing and sizing optimizations[sizing 1].

Repetitive event-rule systems (RER) add feedback by folding the trace back on itself, marking the fold point with a tick mark[sizing 1]. Extended event-rule systems (XER) add disjunction[sizing 2].

Production rule set (PRS)

Main article: Production (computer science)

A production rule specifies either the pull-up or pull-down network of a gate in a QDI circuit and follows the syntax G -> S in which G is a guard as described above and S is one or more dataless assignments in parallel as described above. In states not covered by the guards, it is assumed that the assigned nodes remain at their previous states. This can be achieved using a staticizor of either weak or combinational feedback (shown in red). The most basic example is the C-element in which the guards do not cover the states where A and B are not the same value.

CMOS NAND gate 
A & B -> Out-
~A | ~B -> Out+
CMOS C-element with weak feedback 
A & B -> _O-
~A & ~B -> _O+
_O -> O-
~_O -> O+
CMOS C-element with combinational feedback 
A & B -> _O-
~A & ~B -> _O+
_O -> O-
~_O -> O+

Logic families

Dataless weak condition half buffer 
Re & Lr -> _Rr-
~_Rr -> Rr+

Rr -> Le-

~Re & ~Lr -> _Rr+
_Rr -> Rr-

~Rr -> Le+
Dataless pre-charge half buffer 
en & Lr -> _Rr-
~_Rr -> Rr+

Lr & Rr -> _Lv-
~_Lv -> Lv+
Lv -> Le-
~Le & ~Re -> _en+
_en -> en-

~en -> _Rr+
_Rr -> Rr-

~Lr & ~Rr -> _Lv+
_Lv -> Lv-
~Lv -> Le+
Le & Re -> _en-
~_en -> en+

References

Synthesis

  1. ^ Tse, Jonathan; Hill, Benjamin; Manohar, Rajit (May 2013). "A Bit of Analysis on Self-Timed Single-Bit On-Chip Links" (PDF). Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). doi:10.1109/ASYNC.2013.26. {{cite journal}}: Cite journal requires |journal= (help)
  2. ^ Martin, Alain (1991). Synthesis of Asynchronous VLSI Circuits (PDF) (Ph.D.). California Institute of Technology.

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Timing

  1. ^ a b c Martin, Alain J. (1990). "The Limitations to Delay-Insensitivity in Asynchronous Circuits" (PDF). Sixth MIT Conference on Advanced Research in VLSI. MIT Press.
  2. ^ Manohar, Rajit; Martin, Alain (1995). "Quasi-Delay-Insensitive Circuits are Turing-Complete" (PDF). California Institute of Technology. doi:10.7907/Z9H70CV1. {{cite journal}}: Cite journal requires |journal= (help)
  3. ^ Manohar, R.; Moses, Y. (May 2015). "Analyzing Isochronic Forks with Potential Causality" (PDF). 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems: 69–76. doi:10.1109/async.2015.19.
  4. ^ a b Keller, S.; Katelman, M.; Martin, A. J. (May 2009). "A Necessary and Sufficient Timing Assumption for Speed-Independent Circuits" (PDF). 2009 15th IEEE Symposium on Asynchronous Circuits and Systems: 65–76. doi:10.1109/async.2009.27.
  5. ^ LaFrieda, C.; Manohar, R. (May 2009). "Reducing Power Consumption with Relaxed Quasi Delay-Insensitive Circuits" (PDF). 2009 15th IEEE Symposium on Asynchronous Circuits and Systems: 217–226. doi:10.1109/async.2009.9.
  6. ^ Meng, T. H. Y.; Brodersen, R. W.; Messerschmitt, D. G. (November 1989). "Automatic synthesis of asynchronous circuits from high-level specifications". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 8 (11): 1185–1205. doi:10.1109/43.41504. ISSN 0278-0070.
  7. ^ Pastor, E.; Cortadella, J.; Kondratyev, A.; Roig, O. (November 1998). "Structural methods for the synthesis of speed-independent circuits" (PDF). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 17 (11): 1108–1129. doi:10.1109/43.736185. ISSN 0278-0070.
  8. ^ Stevens, K. S.; Ginosar, R.; Rotem, S. (February 2003). "Relative timing" (PDF). IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 11 (1): 129–140. doi:10.1109/tvlsi.2002.801606. ISSN 1063-8210.
  9. ^ Manoranjan, J. V.; Stevens, K. S. (May 2016). "Qualifying Relative Timing Constraints for Asynchronous Circuits" (PDF). 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC): 91–98. doi:10.1109/async.2016.23.

Verification

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Sizing

  1. ^ a b Burns, Steven (1991). Performance Analysis and Optimization of Asynchronous Circuits (Ph.D.). California Institute of Technology.
  2. ^ Lee, Tak-Kwan (1995). A General Approach to Performance Analysis and Optimization of Asynchronous Circuits (Ph.D.). Defense Technical Information Center.

Layout

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Chips

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Tools

Tutorials

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