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===Selected articles===
===Selected articles===


* I. Vaisband, B. Price, S. Kose, Y. Kolla, E. G. Friedman, and J. Fischer, " Distributed LDO Regulators in a 28 nm Power Delivery System," Analog Integrated Circuits and Signal Processing, Volume 83, Issue 3, pp. 295 – 309, 2015.
* I. Vaisband, B. Price, S. Kose, Y. Kolla, E. G. Friedman, and J. Fischer, "Distributed LDO Regulators in a 28 nm Power Delivery System," Analog Integrated Circuits and Signal Processing, Volume 83, Issue 3, pp.&nbsp;295 – 309, 2015.<ref>{{Cite journal|last=Vaisband|first=Inna|last2=Price|first2=Burt|last3=Köse|first3=Selçuk|last4=Kolla|first4=Yesh|last5=Friedman|first5=Eby G.|last6=Fischer|first6=Jeff|date=2015-06-01|title=Distributed LDO regulators in a 28 nm power delivery system|url=https://link.springer.com/article/10.1007/s10470-015-0526-y|journal=Analog Integrated Circuits and Signal Processing|language=en|volume=83|issue=3|pages=295–309|doi=10.1007/s10470-015-0526-y|issn=0925-1030}}</ref>
* I. Vaisband and E. G. Friedman, " Energy Efficient Clustering of On-Chip Power Delivery Systems," Integration, the VLSI Journal, Volume 48, pp.&nbsp;1 – 9, 2015.
* I. Vaisband and E. G. Friedman, "Energy Efficient Clustering of On-Chip Power Delivery Systems," Integration, the VLSI Journal, Volume 48, pp.&nbsp;1 – 9, 2015.<ref>{{Cite journal|last=Vaisband|first=Inna|last2=Friedman|first2=Eby G.|date=2015|title=Energy efficient adaptive clustering of on-chip power delivery systems|url=https://pdfs.semanticscholar.org/e0f6/727809048fbcfc5428273c527a78a4718ed8.pdf|journal=INTEGRATION, the VLSI journal|volume=48|pages=1-9|via=}}</ref>
* M. Kazemi, E. Ipek, and E. G. Friedman, " Adaptive Compact Magnetic Tunnel Junction Model," IEEE Transactions on Electron Devices, Vol. 61, No. 11, pp.&nbsp;3883–3891, November 2014.
* M. Kazemi, E. Ipek, and E. G. Friedman, "Adaptive Compact Magnetic Tunnel Junction Model," IEEE Transactions on Electron Devices, Vol. 61, No. 11, pp.&nbsp;3883–3891, November 2014.<ref>{{Cite journal|last=Kazemi|first=M.|last2=Ipek|first2=E.|last3=Friedman|first3=E. G.|date=November 2014|title=Adaptive Compact Magnetic Tunnel Junction Model|url=http://ieeexplore.ieee.org/document/6930849/|journal=IEEE Transactions on Electron Devices|volume=61|issue=11|pages=3883–3891|doi=10.1109/TED.2014.2359627|issn=0018-9383}}</ref>
* S. Kvatinsky, N. Wald, G. Satat, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 10, pp.&nbsp;2054–2066, October 2014.
* S. Kvatinsky, N. Wald, G. Satat, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 10, pp.&nbsp;2054–2066, October 2014.<ref>{{Cite journal|last=Kvatinsky|first=S.|last2=Satat|first2=G.|last3=Wald|first3=N.|last4=Friedman|first4=E. G.|last5=Kolodny|first5=A.|last6=Weiser|first6=U. C.|date=October 2014|title=Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies|url=http://ieeexplore.ieee.org/document/6617731/|journal=IEEE Transactions on Very Large Scale Integration (VLSI) Systems|volume=22|issue=10|pages=2054–2066|doi=10.1109/TVLSI.2013.2282132|issn=1063-8210}}</ref>
* A. Shapiro and E. G. Friedman, "MOS Current Mode Logic Near Threshold Circuits," Journal on Low Power Electronics and Applications, Volume 4, pp.&nbsp;138 – 152, 2014.
* A. Shapiro and E. G. Friedman, "MOS Current Mode Logic Near Threshold Circuits," Journal on Low Power Electronics and Applications, Volume 4, pp.&nbsp;138 – 152, 2014.<ref>{{Cite journal|last=Shapiro|first=Alexander|last2=Friedman|first2=Eby G.|date=2014-06-11|title=MOS Current Mode Logic Near Threshold Circuits|url=http://www.mdpi.com/2079-9268/4/2/138|journal=Journal of Low Power Electronics and Applications|language=en|volume=4|issue=2|pages=138–152|doi=10.3390/jlpea4020138}}</ref>
* R. Patel, E. Ipek, and E. G. Friedman, "2T - 1R STT-MRAM Memory Cells for Enhanced Sense Margin and On/Off Current Ratio," Microelectronics Journal, Volume 45, Issue 2, pp.&nbsp;133 – 143, February 2014.
* R. Patel, E. Ipek, and E. G. Friedman, "2T - 1R STT-MRAM Memory Cells for Enhanced Sense Margin and On/Off Current Ratio," Microelectronics Journal, Volume 45, Issue 2, pp.&nbsp;133 – 143, February 2014.<ref>{{Cite journal|date=2014-02-01|title=2T–1R STT-MRAM memory cells for enhanced on/off current ratio|url=https://www.sciencedirect.com/science/article/pii/S0026269213002899|journal=Microelectronics Journal|volume=45|issue=2|pages=133–143|doi=10.1016/j.mejo.2013.11.015|issn=0026-2692}}</ref>
* S. Kvatinsky, Y. H. Nacson, Y. Etsion, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memristor-Based Multithreading," IEEE Computer Architecture Letters, Vol. 13, No. 1, pp.&nbsp;41 – 44, January–June 2014.<ref>{{Cite journal|last=Kvatinsky|first=S.|last2=Nacson|first2=Y. H.|last3=Etsion|first3=Y.|last4=Friedman|first4=E. G.|last5=Kolodny|first5=A.|last6=Weiser|first6=U. C.|date=January 2014|title=Memristor-Based Multithreading|url=http://ieeexplore.ieee.org/document/6489970/|journal=IEEE Computer Architecture Letters|volume=13|issue=1|pages=41–44|doi=10.1109/L-CA.2013.3|issn=1556-6056}}</ref>
* S. Kvatinsky, Y. H. Nacson, Y. Etsion, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memristor-Based Multithreading," IEEE Computer Architecture Letters, Vol. 13, No. 1, pp.&nbsp;41 – 44, January–June 2014.<ref>{{Cite journal|last=Kvatinsky|first=S.|last2=Nacson|first2=Y. H.|last3=Etsion|first3=Y.|last4=Friedman|first4=E. G.|last5=Kolodny|first5=A.|last6=Weiser|first6=U. C.|date=January 2014|title=Memristor-Based Multithreading|url=http://ieeexplore.ieee.org/document/6489970/|journal=IEEE Computer Architecture Letters|volume=13|issue=1|pages=41–44|doi=10.1109/L-CA.2013.3|issn=1556-6056}}</ref>
* Friedman, Eby G. "Clock distribution networks in synchronous digital integrated circuits." Proceedings of the IEEE 89.5 (2001): 665-692.<ref name="autogenerated1">{{cite web|url=http://www.eecs.wsu.edu/~ee587/reference_reading/Friedman_2.pdf|title=Clock Distribution Networks in Synchronous Digital Integrated Circuits|author=Eby G. Friedman|publisher=Eecs.wsu.edu|format=PDF|accessdate=2014-07-14}}</ref>
* Friedman, Eby G. "Clock distribution networks in synchronous digital integrated circuits." Proceedings of the IEEE 89.5 (2001): 665-692.<ref name="autogenerated1">{{cite web|url=http://www.eecs.wsu.edu/~ee587/reference_reading/Friedman_2.pdf|title=Clock Distribution Networks in Synchronous Digital Integrated Circuits|author=Eby G. Friedman|publisher=Eecs.wsu.edu|format=PDF|accessdate=2014-07-14}}</ref>

Revision as of 22:13, 14 December 2017

Eby G. Friedman
Friedman in 2008
Born (1957-08-10) 10 August 1957 (age 66)
Jersey City, New Jersey
EducationLafayette College
University of California, Irvine
AwardsIEEE Fellow
IEEE CAS Charles A. Desoer Technical Achievement Award
Fulbright Scholar
University of California, Irvine Engineering Hall of Fame
Scientific career
FieldsElectrical and Computer Engineering
InstitutionsUniversity of Rochester
Technion – Israel Institute of Technology
Hughes Aircraft Company
Doctoral advisorJames H. Mulligan, Jr.
Websitewww.ece.rochester.edu/~friedman

Eby G. Friedman is an electrical engineer, and Distinguished Professor of Electrical and Computer Engineering at the University of Rochester. Friedman is also a Visiting Professor at the Technion - Israel Institute of Technology. He is a Senior Fulbright Fellow and a Fellow of the IEEE.

Early life and education

Born in Jersey City, New Jersey, in 1957,[1] he earned an electrical engineering baccalaureate degree from Lafayette College in 1979, a master's degree (1981) and a doctoral degree (1989) from the University of California, Irvine, also in electrical engineering.[2] Friedman married his wife Laurie Friedman in 1984, and they have two sons.[3]

Career

Friedman's research interests include integrated circuits, VLSI design and analysis, clock synchronization, power delivery, 3-D integration, and mixed-signal circuits.[4]

His career began in the Netherlands in 1978, working at Philips Gloeilampen Fabreiken on designing bipolar differential amplifiers.[1] From 1979–1991 he worked at Hughes Aircraft Company.[5] He joined the Electrical and Computer Engineering faculty at the University of Rochester in 1991.[5]

He received the 2005 William H. Riker University Award for Graduate Teaching at the University of Rochester.[6] In 2012 he became a Distinguished Lecturer of the IEEE CAS Society,[citation needed] and in 2013, he was awarded the Charles A. Desoer Technical Achievement Award, as a Fellow of the IEEE.[7] In October 2015 he was inducted into the University of California, Irvine, Engineering Hall of Fame.[8]

Service

Editing

Friedman serves as editor-in-chief of the Microelectronics Journal[9] and is a member of the editorial board of the Journal of Low Power Electronics and Applications.[10] He is a past editor-in-chief and chair of the steering committee for the IEEE Transactions on Very Large Scale Integration (VLSI) Systems[11] as well as past regional editor of the Journal of Circuits, Systems and Computers.[12] He formerly served as a member of several editorial boards: the Analog Integrated Circuits and Signal Processing,[12] the Journal of VLSI Signal Processing,[citation needed] and the Proceedings of the IEEE and IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing.[citation needed]

Committee work

Friedman has served multiple IEEE societies and committees: Circuits and Systems (CAS) Society Board of Governors and CAS liaison to the Solid-State Circuits Society (SSCS);[citation needed] past chair of the VLSI Systems and Applications Circuits and Systems Society Technical Committee;[13] and past chair of the Electron Devices Chapter of the Rochester Section.[citation needed]

Selected workshops and conferences

He was General/Program/Technical Co-Chair,for the 1997 International Workshop on Clock Distribution Networks.[14][dead link] He has also chaired the following IEEE events: the 2000 Workshop on Signal Processing Systems,[15] the 2003 and 2004 IEEE International Workshop on System-on-Chip for Real-Time Applications,[16] the 2004 IEEE International Conference on Electronics, Circuits, and Systems,[citation needed] the 2006 IEEE International Symposium on Circuits and Systems,[17][dead link] and the 2007 IEEE International Symposium on Networks on Chip (NoC).[18]

Publications and patents

Friedman has published almost 500 papers[19] and is co-inventor of 13 patents.[20]

Books / chapters

  • Clock Distribution Networks in VLSI Circuits and Systems (IEEE Press, 1995)[21]
  • High Performance Clock Distribution Networks (Kluwer Academic Publishers, 1997)[22]
  • Analog Design Issues in Digital VLSI Circuits and Systems (Kluwer Academic Publishers, 1997)[23]
  • Timing Optimization through Clock Skew Scheduling ( 2000 and 2009)(first and second edition)[23]
  • On-Chip Inductance in High Speed Integrated Circuits (Kluwer Academic Publishers, 2001)[24]
  • Power Distribution Networks in High Speed Integrated Circuits (Kluwer Academic Publishers, 2004)[25]
  • Multi-Voltage CMOS Circuit Design (John Wiley & Sons Press, 2006)[26]
  • Power Distribution Networks with On-Chip Decoupling Capacitors (Springer Verlag, 2008 and 2011)(first and second edition) [27]
  • Three-Dimensional Integrated Circuit Design (Morgan Kaufmann, 2009)[28]
  • High Performance Integrated Circuit Design (McGraw-Hill Publishers, 2012) [29]
  • J. Rosenfeld and E. G. Friedman, On-Chip Resonance in Nanoscale Integrated Circuits: Design and Analysis Methodologies for Advanced Data, Clock, and Power Generation Networks[30]

Selected articles

  • I. Vaisband, B. Price, S. Kose, Y. Kolla, E. G. Friedman, and J. Fischer, "Distributed LDO Regulators in a 28 nm Power Delivery System," Analog Integrated Circuits and Signal Processing, Volume 83, Issue 3, pp. 295 – 309, 2015.[31]
  • I. Vaisband and E. G. Friedman, "Energy Efficient Clustering of On-Chip Power Delivery Systems," Integration, the VLSI Journal, Volume 48, pp. 1 – 9, 2015.[32]
  • M. Kazemi, E. Ipek, and E. G. Friedman, "Adaptive Compact Magnetic Tunnel Junction Model," IEEE Transactions on Electron Devices, Vol. 61, No. 11, pp. 3883–3891, November 2014.[33]
  • S. Kvatinsky, N. Wald, G. Satat, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 10, pp. 2054–2066, October 2014.[34]
  • A. Shapiro and E. G. Friedman, "MOS Current Mode Logic Near Threshold Circuits," Journal on Low Power Electronics and Applications, Volume 4, pp. 138 – 152, 2014.[35]
  • R. Patel, E. Ipek, and E. G. Friedman, "2T - 1R STT-MRAM Memory Cells for Enhanced Sense Margin and On/Off Current Ratio," Microelectronics Journal, Volume 45, Issue 2, pp. 133 – 143, February 2014.[36]
  • S. Kvatinsky, Y. H. Nacson, Y. Etsion, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memristor-Based Multithreading," IEEE Computer Architecture Letters, Vol. 13, No. 1, pp. 41 – 44, January–June 2014.[37]
  • Friedman, Eby G. "Clock distribution networks in synchronous digital integrated circuits." Proceedings of the IEEE 89.5 (2001): 665-692.[38]
  • Ismail, Yehea, and Eby G. Friedman. "Effects of inductance on the propagation delay and repeater insertion in VLSI circuits." Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 8.2 (2000): 195-206.[39]
  • Ismail, Yehea, Eby G. Friedman, and Jose L. Neves. "Figures of merit to characterize the importance of on-chip inductance." Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 7.4 (1999): 442-449.[40]
  • Hauryla, Mikhail, et al. "On-chip optical interconnect roadmap: challenges and critical directions." Selected Topics in Quantum Electronics, IEEE Journal of12.6 (2006): 1699-1705.[41]

References

  1. ^ a b "Eby G. Friedman's Homepage". www2.ece.rochester.edu. Retrieved 2017-12-13.
  2. ^ "Manhattan Routing Welcomes Eby Friedman, IEEE Fellow and Distinguished Professor at the University of Rochester, to Technical Advisory Board". www.businesswire.com. 2004-06-07. Retrieved 2017-12-13. {{cite web}}: Cite has empty unknown parameter: |dead-url= (help)
  3. ^ "Connecticut Marriage Index, 1959-2012". Ancestry.com. 10 June 1984. Retrieved 2017-12-13. {{cite web}}: Cite has empty unknown parameter: |dead-url= (help); Unknown parameter |subscription= ignored (|url-access= suggested) (help)
  4. ^ "Directory: Electrical and Computer Engineering". Ece.rochester.edu. Retrieved 2015-12-17. {{cite web}}: Cite has empty unknown parameter: |dead-url= (help)
  5. ^ a b Friedman, Eby (2009). "Design Challenges in High Performance Three-Dimensional Circuits" (PDF). semanticscholar.org. {{cite web}}: Cite has empty unknown parameter: |dead-url= (help)
  6. ^ "William H. Riker University Award for Excellence in Graduate Teaching". www.rochester.edu. Office of the Provost, University of Rochester. Retrieved 2017-12-13. {{cite web}}: Cite has empty unknown parameter: |dead-url= (help)
  7. ^ "Charles A. Desoer Technical Achievement Award | IEEE Circuits and Systems Society". Ieee-cas.org. Archived from the original on 2016-02-23. Retrieved 2015-07-14. {{cite web}}: Unknown parameter |deadurl= ignored (|url-status= suggested) (help)
  8. ^ "2015 Hall of Fame Inductees | The Henry Samueli School of Engineering at UC Irvine". engineering.uci.edu. Retrieved 2017-12-13. {{cite web}}: Cite has empty unknown parameter: |dead-url= (help)
  9. ^ "Microelectronics Journal Editorial Board". elsevier.com. Retrieved 2015-07-14. {{cite web}}: Cite has empty unknown parameter: |dead-url= (help)
  10. ^ "Editors of JLPEA". MDPI. Retrieved 2017-05-08.
  11. ^ "Past Editors in Chief - IEEE CAS". ieee-cas.org. Retrieved 2017-12-13. {{cite web}}: Cite has empty unknown parameter: |dead-url= (help)
  12. ^ a b "Power Delivery in Heterogeneous Nanoscale Integrated Circuits | EE". www.ee.ucla.edu. Retrieved 2017-12-13.
  13. ^ "Officers and Members". ieee-cas.org. Retrieved 2015-07-14. {{cite web}}: Cite has empty unknown parameter: |dead-url= (help)
  14. ^ "Publications search" (PDF). springer.com. Retrieved 2015-07-14.
  15. ^ "2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS". IEEE. October 2000. Retrieved 2015-07-14. {{cite web}}: Cite has empty unknown parameter: |dead-url= (help)
  16. ^ "4th IEEE International Workshop on System-on-Chip for Real-Time Applications". IEEE. 2004. Retrieved 2015-07-14. {{cite web}}: Cite has empty unknown parameter: |dead-url= (help)
  17. ^ "Publications search" (PDF). ieee-cas.org. Retrieved 2015-07-14.
  18. ^ "Message from the general and program chairs". NOCS2007. IEEE. 2007. Retrieved 2015-07-14. {{cite web}}: Cite has empty unknown parameter: |dead-url= (help)
  19. ^ "Eby G. Friedman/Publications". Retrieved 2014-07-14. {{cite web}}: Cite has empty unknown parameter: |dead-url= (help)
  20. ^ "Eby G. Friedman/Patents". www2.ece.rochester.edu. Retrieved 2017-12-13. {{cite web}}: Cite has empty unknown parameter: |dead-url= (help)
  21. ^ Eby G. Friedman (1995). Clock distribution networks in VLSI circuits and systems. Institute of Electrical and Electronics Engineers. ISBN 978-0-7803-1058-2.
  22. ^ Eby G. Friedman (6 December 2012). High Performance Clock Distribution Networks. Springer Science & Business Media. ISBN 978-1-4684-8440-3.
  23. ^ a b Juan J. Becerra; Eby G. Friedman (6 December 2012). Analog Design Issues in Digital VLSI Circuits and Systems: A Special Issue of Analog Integrated Circuits and Signal Processing, An International Journal Volume 14, Nos. 1/2 (1997). Springer Science & Business Media. ISBN 978-1-4615-6101-9.
  24. ^ "On-Chip Inductance in High-Speed Integrated Circuits" (PDF). Ece.northwestern.edu. Retrieved 2014-07-14.
  25. ^ Power Distribution Networks in High Speed Integrated | Andrey V. Mezhiba | Springer.
  26. ^ Kursun, Volkan; Friedman, Eby G. Multi-Voltage CMOS Circuit Design - Kursun - Wiley Online Library. doi:10.1002/0470033371.
  27. ^ Mikhail Popovich; Andrey V. Mezhiba; Selçuk Köse; Eby Friedman. "Power Distribution Networks with On-Chip Decoupling Capacitors" (PDF). Ihome.ust.hk. Retrieved 2014-07-14.
  28. ^ F. Pavlidis; Eby G. Friedman. "Three-Dimensional Integrated Circuit Design". Elsevier Inc. Retrieved 2014-07-14.
  29. ^ Emre Salman; Eby Friedman. "High Performance Integrated Circuit Design". McGraw Hill Professional. Retrieved 2014-07-14.
  30. ^ J. Rosenfeld; E. G. Friedman. "On-Chip Resonance in Nanoscale Integrated Circuits" (PDF). Lambert Academic. Retrieved 2014-07-14.
  31. ^ Vaisband, Inna; Price, Burt; Köse, Selçuk; Kolla, Yesh; Friedman, Eby G.; Fischer, Jeff (2015-06-01). "Distributed LDO regulators in a 28 nm power delivery system". Analog Integrated Circuits and Signal Processing. 83 (3): 295–309. doi:10.1007/s10470-015-0526-y. ISSN 0925-1030.
  32. ^ Vaisband, Inna; Friedman, Eby G. (2015). "Energy efficient adaptive clustering of on-chip power delivery systems" (PDF). INTEGRATION, the VLSI journal. 48: 1–9.
  33. ^ Kazemi, M.; Ipek, E.; Friedman, E. G. (November 2014). "Adaptive Compact Magnetic Tunnel Junction Model". IEEE Transactions on Electron Devices. 61 (11): 3883–3891. doi:10.1109/TED.2014.2359627. ISSN 0018-9383.
  34. ^ Kvatinsky, S.; Satat, G.; Wald, N.; Friedman, E. G.; Kolodny, A.; Weiser, U. C. (October 2014). "Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies". IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22 (10): 2054–2066. doi:10.1109/TVLSI.2013.2282132. ISSN 1063-8210.
  35. ^ Shapiro, Alexander; Friedman, Eby G. (2014-06-11). "MOS Current Mode Logic Near Threshold Circuits". Journal of Low Power Electronics and Applications. 4 (2): 138–152. doi:10.3390/jlpea4020138.{{cite journal}}: CS1 maint: unflagged free DOI (link)
  36. ^ "2T–1R STT-MRAM memory cells for enhanced on/off current ratio". Microelectronics Journal. 45 (2): 133–143. 2014-02-01. doi:10.1016/j.mejo.2013.11.015. ISSN 0026-2692.
  37. ^ Kvatinsky, S.; Nacson, Y. H.; Etsion, Y.; Friedman, E. G.; Kolodny, A.; Weiser, U. C. (January 2014). "Memristor-Based Multithreading". IEEE Computer Architecture Letters. 13 (1): 41–44. doi:10.1109/L-CA.2013.3. ISSN 1556-6056.
  38. ^ Eby G. Friedman. "Clock Distribution Networks in Synchronous Digital Integrated Circuits" (PDF). Eecs.wsu.edu. Retrieved 2014-07-14.
  39. ^ Ismail, Y. I.; Friedman, E. G. (April 2000). "Effects of inductance on the propagation delay and repeater insertion in VLSI circuits". IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 8 (2): 195–206. doi:10.1109/92.831439. ISSN 1063-8210.
  40. ^ Ismail, Y. I.; Friedman, E. G.; Neves, J. L. (June 1998). "Figures of merit to characterize the importance of on-chip inductance". Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175): 560–565. doi:10.1145/277044.277193.
  41. ^ Haurylau, M.; Chen, G.; Chen, H.; Zhang, J.; Nelson, N. A.; Albonesi, D. H.; Friedman, E. G.; Fauchet, P. M. (November 2006). "On-Chip Optical Interconnect Roadmap: Challenges and Critical Directions". IEEE Journal of Selected Topics in Quantum Electronics. 12 (6): 1699–1705. doi:10.1109/JSTQE.2006.880615. ISSN 1077-260X.
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