Nader Bagherzadeh: Difference between revisions
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==Notable Works== |
==Notable Works== |
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*MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications <ref>{{cite journal|last1=Singh|first1=H.|last2=Ming-Hau Lee|last3=Guangming Lu|last4=Kurdahi|first4=F.J.|last5=Bagherzadeh|first5=N.|last6=Chaves Filho|first6=E.M.|title=MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications|journal=IEEE Transactions on Computers|date=May 2000|volume=49|issue=5|pages=465–481|url=https://doi.org/10.1109/12.859540}}</ref> |
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*[https://link.springer.com/chapter/10.1007/978-1-4615-4417-3_3 Design and implementation of the MorphoSys reconfigurable computing processor] |
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*Design and implementation of the MorphoSys reconfigurable computing processor <ref>{{cite journal|last1=Lee|first1=Ming-Hau|last2=Singh|first2=Hartej|last3=Lu|first3=Guangming|last4=Bagherzadeh|first4=Nader|last5=Kurdahi|first5=Fadi J.|last6=Filho|first6=Eliseu M. C.|last7=Alves|first7=Vladimir Castro|title=Design and Implementation of the MorphoSys Reconfigurable Computing Processor|journal=Field-Programmable Custom Computing Technology: Architectures, Tools, and Applications|date=2000|pages=21–38|doi=10.1007/978-1-4615-4417-3_3|url=https://doi.org/10.1007/978-1-4615-4417-3_3|publisher=Springer, Boston, MA|language=en}}</ref> |
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*[https://dl.acm.org/citation.cfm?id=379076 Power-aware scheduling under timing constraints for mission-critical embedded systems] |
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*Power-aware scheduling under timing constraints for mission-critical embedded systems <ref>{{cite journal|last1=Liu|first1=Jinfeng|last2=Chou|first2=Pai H.|last3=Bagherzadeh|first3=Nader|last4=Kurdahi|first4=Fadi|title=Power-aware Scheduling Under Timing Constraints for Mission-critical Embedded Systems|journal=Proceedings of the 38th Annual Design Automation Conference|date=2001|pages=840–845|doi=10.1145/378239.379076|url=http://doi.acm.org/10.1145/378239.379076|publisher=ACM}}</ref> |
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*Optimal Ring Embedding in Hypercubes with Faulty Links |
*Optimal Ring Embedding in Hypercubes with Faulty Links |
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==Awards== |
==Awards== |
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Revision as of 22:55, 9 January 2018
Nader Bagherzadeh | |
|---|---|
 Professor Nader Bagherzadeh | |
| Nationality | Iranian, American |
| Occupation(s) | Academic, Researcher |
| Academic background | |
| Alma mater | University of Texas, Austin |
| Academic work | |
| Institutions | University of California, Irvine |
| Main interests | Computer Architecture, Network-on-Chip |
| Website | http://engineering.uci.edu/users/nader-bagherzadeh |
Nader Bagherzadeh ( Persian: نادر باقرزاده ) is a professor of Computer Engineering in the Department of Electrical Engineering and Computer Science at the University of California, Irvine, where he served as a chair from 1998 to 2003. Professor Bagherzadeh has been involved in research and development in the areas of: Computer Architecture, Reconfigurable Computing, VLSI Chip Design, Network-on-Chip, 3D chips, Sensor Networks, Computer Graphics, Memory and Embedded Systems, since he received a Ph.D. degree from the University of Texas at Austin in 1987. He is a Fellow of the IEEE. Professor Bagherzadeh has published more than 300 articles in peer-reviewed journals and conferences. His former students have assumed key positions in software and computer systems design companies in the past thirty years. He has been a PI or Co-PI of research grants for developing all aspects of next generation computer systems for embedded systems as well as general purpose computing.
Nader Bagherzadeh from the University of California, Irvine was named Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in 2014[1] for contributions to the design and analysis of coarse-grained reconfigurable processor architectures. He was with AT&T Bell Labs from 1980 to 1984.
Education
- PhD, 1987 Computer Engineering University of Texas-Austin
- MS, 1979 Electrical Engineering University of Texas-Austin
- BS, 1977 Electrical Engineering University of Texas-Austin
Notable Works
- MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications [2]
- Design and implementation of the MorphoSys reconfigurable computing processor [3]
- Power-aware scheduling under timing constraints for mission-critical embedded systems [4]
- Optimal Ring Embedding in Hypercubes with Faulty Links
Awards
- 2002, Best paper award in IEEE Transactions on VLSI Design (TVLSI)
- 2002, Best paper award in the proceedings of Asia and South Pacific Design Automation Conference (ASPDAC)
References
- ^ "2014 elevated fellow". IEEE Fellows Directory.
{{cite web}}: Cite has empty unknown parameter:|dead-url=(help) - ^ Singh, H.; Ming-Hau Lee; Guangming Lu; Kurdahi, F.J.; Bagherzadeh, N.; Chaves Filho, E.M. (May 2000). "MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications". IEEE Transactions on Computers. 49 (5): 465–481.
- ^ Lee, Ming-Hau; Singh, Hartej; Lu, Guangming; Bagherzadeh, Nader; Kurdahi, Fadi J.; Filho, Eliseu M. C.; Alves, Vladimir Castro (2000). "Design and Implementation of the MorphoSys Reconfigurable Computing Processor". Field-Programmable Custom Computing Technology: Architectures, Tools, and Applications. Springer, Boston, MA: 21–38. doi:10.1007/978-1-4615-4417-3_3.
- ^ Liu, Jinfeng; Chou, Pai H.; Bagherzadeh, Nader; Kurdahi, Fadi (2001). "Power-aware Scheduling Under Timing Constraints for Mission-critical Embedded Systems". Proceedings of the 38th Annual Design Automation Conference. ACM: 840–845. doi:10.1145/378239.379076.
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