Bumpless Build-up Layer
|This article is an orphan, as no other articles link to it. Please introduce links to this page from ; try the Find links tool for suggestions. (February 2009)|
Bumpless Build-up Layer or BBUL is a processor packaging technology developed by Intel. It is bumpless, because it does not use the usual tiny solder bumps to attach the silicon die to the processor package wires. It has build-up layers, because is grown or built up around the silicon die. The usual way is to manufacture them separately and bond them together.
It was presented in October 2001. It should have been a key component in the 8 GHz and 15 GHz processors that should have been in the market by 2005 and 2007 respectively. Also 20 GHz should have been possible before the year 2010. The BBUL is not needed yet[when?] because there is no longer the clock-frequency competition.
- Thinner and lighter.
- Higher performance and lower power.
- Higher interconnect density. C4 bumps were reaching their limits.
- Better signal routing capability.
- Allows many chips in the same package.
- BBUL Packaging[dead link]
- Intel to delay Bumpless Build-up Layer processor package
- Bumpless Build-Up Layer Packaging
|This microcomputer/microprocessor–related article is a stub. You can help Wikipedia by expanding it.|