Fan-out

In digital electronics, the fan-out is the number of gate inputs driven by the output of another single logic gate.

In most designs, logic gates are connected to form more complex circuits. While no logic gate input can be fed by more than one output at a time without causing contention, it is common for one output to be connected to several inputs. The technology used to implement logic gates usually allows a certain number of gate inputs to be wired directly together without additional interfacing circuitry. The maximum fan-out of an output measures its load-driving capability: it is the greatest number of inputs of gates of the same type to which the output can be safely connected.

Logical practice

Maximum limits on fan-out are usually stated for a given logic family or device in the manufacturer's datasheets. These limits assume that the driven devices are members of the same family.

More complex analysis than fan-in and fan-out is required when two different logic families are interconnected. Fan-out is ultimately determined by the maximum source and sink currents of an output and the maximum source and sink currents of the connected inputs; the driving device must be able to supply or sink at its output the sum of the currents needed or provided (depending on whether the output is a logic high or low voltage level) by all of the connected inputs, while maintaining the output voltage specifications. For each logic family, typically a "standard" input is defined by the manufacturer with maximum input currents at each logic level, and the fan-out for an output is computed as the number of these standard inputs that can be driven in the worst case. (Therefore, it is possible that an output can actually drive more inputs than specified by fan-out, even of devices within the same family, if the particular devices being driven sink and/or source less current, as reported on their data sheets, than a "standard" device of that family.) Ultimately, whether a device has the fan-out capability to drive (with guaranteed reliability) a set of inputs is determined by adding up all the input-low (max.) source currents specified on the datasheets of the driven devices, adding up all the input-high (max.) sink currents of those same devices, and comparing those sums to the driving device's guaranteed maximum output-low sink current and output-high source current specifications, respectively. If both totals are within the driving device's limits, then it has the DC fan-out capacity to drive those inputs on those devices as a group, and otherwise it doesn't, regardless of the manufacturer's given fan-out number. However, for any reputable manufacturer, if this current analysis reveals that the device cannot drive the inputs, the fan-out number will agree.

When high-speed signal switching is required, the AC impedance of the output, the inputs, and the conductors between may significantly reduce the effective drive capacity of output, and this DC analysis may not be enough. See AC Fan-out below.

Theory

DC fan-out

A perfect logic gate would have infinite input impedance and zero output impedance, allowing a gate output to drive any number of gate inputs. However, since real-world fabrication technologies exhibit less than perfect characteristics, a limit will be reached where a gate output cannot drive any more current into subsequent gate inputs - attempting to do so causes the voltage to fall below the level defined for the logic level on that wire, causing errors.

The fan-out is the number of inputs that can be connected to an output before the current required by the inputs exceeds the current that can be delivered by the output while still maintaining correct logic levels. The current figures may be different for the logic zero and logic one states and in that case we must take the pair that give the lower fan-out. This can be expressed mathematically as

{\text{DC Fan-out}}=\operatorname {min} \left(\left\lfloor {\frac {I_{\text{out high}}}{I_{\text{in high}}}}\right\rfloor ,\left\lfloor {\frac {I_{\text{out low}}}{I_{\text{in low}}}}\right\rfloor \right)

where $\lfloor \;\rfloor$ is the floor function.

Going on these figures alone TTL logic gates are limited to perhaps 2 to 10, depending on the type of gate, while CMOS gates have DC fan-outs that are generally far higher than is likely to occur in practical circuits (e.g. using NXP Semiconductor specifications for their HEF4000 series CMOS chips at 25 °C and 15 V gives a fan-out of 34 000).

AC fan-out

However, inputs of real gates have capacitance as well as resistance to the power supply rails. This capacitance will slow the output transition of the previous gate and hence increase its propagation delay. As a result, rather than a fixed fan-out the designer is faced with a trade off between fan-out and propagation delay (which affects the maximum speed of the overall system). This effect is less marked for TTL systems, which is one reason why TTL maintained a speed advantage over CMOS for many years.

Often a single signal (as an extreme example, the clock signal) needs to drive far more than 10 things on a chip. Rather than simply wiring the output of a gate to 1000 different inputs, circuit designers have found that it runs much faster to have a tree (as an extreme example, a clock tree) – for example, have the output of that gate drive 10 buffers (or equivalently a buffer scaled 10 times as big as the minimum-size buffer), those buffers drive 100 other buffers (or equivalently a buffer scaled 100 times as big as the minimum-size buffer), and those final buffers to drive the 1000 desired inputs. During physical design, some VLSI design tools do buffer insertion as part of signal integrity design closure.

Likewise, rather than simply wiring all 64 output bits to a single 64-input NOR gate to generate the Z flag on a 64-bit ALU, circuit designers have found that it runs much faster to have a tree – for example, have the Z flag generated by an 8-input NOR gate, and each of their inputs generated by an 8-input OR gate.

Reminiscent of radix economy, one estimate for the total delay of such a tree—the total number of stages by the delay of each stage – gives an optimum (minimum delay) when each stage of the tree is scaled by e, approximately 2.7. People who design digital integrated circuits typically insert trees whenever necessary such that the fan-in and fan-out of each and every gate on the chip is between 2 and 10.^[1]

Dynamic or AC fan-out, not DC fan-out is therefore the primary limiting factor in many practical cases, due to the speed limitation. For example, suppose a microcontroller has 3 devices on its address and data lines, and the microcontroller can drive 35 pF of bus capacitance at its maximum clock speed. If each device has 8 pF of input capacitance, then only 11 pF of trace capacitance is allowable. (Routing traces on printed circuit boards usually have 1-2 pF per inch so the traces in this case can be 5.5 inches long max.) If this trace length condition can't be met, then the microcontroller must be run at a slower bus speed for reliable operation, or a buffer chip with higher current drive must be inserted into the circuit. Higher current drive increases speed since $\textstyle \ I=C{\frac {dV}{dt}}$ ; more simply, current is rate of flow of charge, so increased current charges the capacitance faster, and the voltage across a capacitor is equal to the charge on it divided by the capacitance. So with more current, voltage changes faster, which allows faster signaling over the bus.

Unfortunately, due to the higher speeds of modern devices, IBIS simulations may be required for exact determination of the dynamic fan-out since dynamic fan-out is not clearly defined in most datasheets. (See the external link for more information.)

References

^ Miles Murdocca, Apostolos Gerasoulis, and Saul Levy. "Novel Optical Computer Architecture Utilizing Reconfigurable Interconnects". 1991. p. 60-61.

External links

HIGH-SPEED DIGITAL DESIGN — online newsletter — Vol. 8 Issue 07

[1] Miles Murdocca, Apostolos Gerasoulis, and Saul Levy. "Novel Optical Computer Architecture Utilizing Reconfigurable Interconnects". 1991. p. 60-61.

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