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An inter-processor interrupt (IPI) is a special type of interrupt by which one processor may interrupt another processor in a multiprocessor system. IPIs are typically used to implement a cache coherency synchronization point.
IPI signalling is often performed through the use of the APIC. When a CPU wishes to send an interrupt to another CPU, it stores the interrupt vector and the identifier of the target's local APIC in the Interrupt Command Register (ICR) of its own local APIC. A message is then sent via the APIC bus to the target's local APIC, which therefore issues a corresponding interrupt to its own CPU.
In a Microsoft Windows based multiprocessor system, a processor may interrupt another processor for the following reasons:
1. Queue a DISPATCH_LEVEL interrupt to schedule a particular thread for execution.
2. Updating the processor's translation lookaside buffers cache.
3. System shutdown.
4. System crash.
5. Kernel debugger breakpoint.
IPIs are given an IRQL of 29.
- Advanced Programmable Interrupt Controller (APIC)
- Interrupt handler
- Non-maskable interrupt (NMI)
- Programmable Interrupt Controller (PIC)
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