NAND logic

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This article is about NAND Logic in the sense of building other logic gates using just NAND gates. For NAND Gates, see NAND gate. For NAND in the purely logical sense, see Logical NAND. For logic gates generally, see Logic gate.

Because the NAND function has functional completeness all logic systems can be converted into NAND gates. This is also true of NOR gates. In principle, any combinatorial logic function can be realized with enough NAND gates.

NAND[edit]

A NAND gate is an inverted AND gate. It has the following truth table:

NAND ANSI Labelled.svg

Q = NOT( A AND B )

Truth Table
Input A Input B Output Q
0 0 1
0 1 1
1 0 1
1 1 0

NOT[edit]

A NOT gate is made by joining the inputs of a NAND gate together. Since a NAND gate is equivalent to an AND gate followed by a NOT gate, joining the inputs of a NAND gate leaves only the NOT gate.

Desired NOT Gate NAND Construction
NOT ANSI Labelled.svg NOT from NAND.svg
Q = NOT( A ) = NOT( A AND A )
Truth Table
Input A Output Q
0 1
1 0

AND[edit]

An AND gate is made by following a NAND gate with a NOT gate as shown below. This gives a NOT NAND, i.e. AND.

Desired AND Gate NAND Construction
AND ANSI Labelled.svg AND from NAND.svg
Q = A AND B = NOT[ NOT( A AND B ) AND NOT( A AND B ) ]
Truth Table
Input A Input B Output Q
0 0 0
0 1 0
1 0 0
1 1 1

OR[edit]

If the truth table for a NAND gate is examined or by applying De Morgan's Laws, it can be seen that if any of the inputs are 0, then the output will be 1. To be an OR gate, however, the output must be 1 if any input is 1. Therefore, if the inputs are inverted, any high input will trigger a high output.

Desired OR Gate NAND Construction
OR ANSI Labelled.svg OR from NAND.svg
Q = A OR B = NOT[ NOT( A AND A ) AND NOT( B AND B )]
Truth Table
Input A Input B Output Q
0 0 0
0 1 1
1 0 1
1 1 1

NOR[edit]

A NOR gate is simply an inverted OR gate. Output is high when neither input A nor input B is high:

Desired NOR Gate NAND Construction
NOR ANSI Labelled.svg NOR from NAND.svg
Q = NOT( A OR B ) = NOT{ NOT[ NOT( A AND A ) AND NOT( B AND B )] AND
NOT[ NOT( A AND A ) AND NOT( B AND B )] }
Truth Table
Input A Input B Output Q
0 0 1
0 1 0
1 0 0
1 1 0

XOR[edit]

An XOR gate is constructed similarly to an OR gate, except with an additional NAND gate inserted such that if both inputs are high, the inputs to the final NAND gate will also be high, and the output will be low.

Desired XOR Gate NAND Construction
XOR ANSI Labelled.svg XOR from NAND.svg
Q = A XOR B = NOT{ NOT[ A AND NOT( A AND B ) ] AND
NOT[ B AND NOT( A AND B ) ] }
Truth Table
Input A Input B Output Q
0 0 0
0 1 1
1 0 1
1 1 0

XNOR[edit]

An XNOR gate is simply an XOR gate with an inverted output:

Desired XNOR Gate NAND Construction
XNOR ANSI Labelled.svg XNOR from NAND.svg
Q = NOT( A XOR B) = NOT( NOT{ NOT[ A AND NOT( A AND B ) ] AND
NOT[ B AND NOT( A AND B ) ] } AND
NOT{ NOT[ A AND NOT( A AND B ) ]
AND NOT[ B AND NOT( A AND B ) ] } )
Truth Table
Input A Input B Output Q
0 0 1
0 1 0
1 0 0
1 1 1

See also[edit]

External links[edit]

References[edit]

Lancaster, Don (1974). TTL Cookbook (1st ed.). Indianapolis, IN: Howard W Sams. pp. 126–135. ISBN 0-672-21035-5.